公开(公告)号：US08232659B2

公开(公告)日：2012-07-31

申请号：US12048015

申请日：2008-03-13

Applicant: Hsueh-Chung Chen ,  Chine-Gie Lou ,  Su-Chen Fan

Inventor： Hsueh-Chung Chen ,  Chine-Gie Lou ,  Su-Chen Fan

IPC: H01L23/544 ,  H01L23/34

CPC classification number: H01L21/681

Abstract: Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.

Abstract translation: IC器件基板的对准方法。 第一IC器件衬底具有用于限定多个第一IC特征的第一前侧，与第一前侧相对的第一背面，以及形成在第一前侧或第一背面上的第一对准图案。 第二IC器件衬底具有用于限定多个第二IC特征的第二前侧，与第二前侧相对的第二后侧和形成在第二前侧或第二后侧上的第二对准图案。 应用第一光学检测器和第二光学检测器来检测第一和第二对准图案，以对准第一和第二IC器件基板。 具体地，第一和第二对准图案朝向相反方向的第一和第二光学检测器。

公开(公告)号：US07371663B2

公开(公告)日：2008-05-13

申请号：US11174511

申请日：2005-07-06

Applicant: Hsueh-Chung Chen ,  Chine-Gie Lou ,  Su-Chen Fan

Inventor： Hsueh-Chung Chen ,  Chine-Gie Lou ,  Su-Chen Fan

IPC: H01L21/00

CPC classification number: H01L21/681

Abstract: Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.

Abstract translation: IC器件基板的对准方法。 第一IC器件衬底具有用于限定多个第一IC特征的第一前侧，与第一前侧相对的第一背面，以及形成在第一前侧或第一背面上的第一对准图案。 第二IC器件衬底具有用于限定多个第二IC特征的第二前侧，与第二前侧相对的第二后侧和形成在第二前侧或第二后侧上的第二对准图案。 应用第一光学检测器和第二光学检测器来检测第一和第二对准图案，以对准第一和第二IC器件基板。 具体地，第一和第二对准图案朝向相反方向的第一和第二光学检测器。

公开(公告)号：US07781892B2

公开(公告)日：2010-08-24

申请号：US11317652

申请日：2005-12-22

Applicant: Hsueh-Chung Chen ,  Chine-Gie Lou ,  Ping-Liang Liu ,  Su-Chen Fan

Inventor： Hsueh-Chung Chen ,  Chine-Gie Lou ,  Ping-Liang Liu ,  Su-Chen Fan

IPC: H01L29/41

CPC classification number: H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved interconnect structure and method of making such a device. The improved interconnect electrically connects two otherwise separate areas on a semiconductor wafer. The interconnect preferably uses a copper conductor disposed within a trench and via structure formed in a low-k hybrid dielectric layer using a dual damascene process. Each contact region is served by a plurality of vias, each in communication with the trench conductor portion. The entry from the trench to the via is rounded for at least one and preferably all of the via structures.

Abstract translation: 改进的互连结构和制造这种装置的方法。 改进的互连电路连接半导体晶片上的另外两个分开的区域。 互连优选地使用布置在沟槽内的铜导体和使用双镶嵌工艺在低k混合电介质层中形成的通孔结构。 每个接触区域由多个通孔提供，每个通孔与沟槽导体部分连通。 从沟槽到通孔的入口对于至少一个并且优选地所有通孔结构是圆形的。

公开(公告)号：US20070145596A1

公开(公告)日：2007-06-28

申请号：US11317652

申请日：2005-12-22

Applicant: Hsueh-Chung Chen ,  Chine-Gie Lou ,  Ping-Liang Liu ,  Su-Chen Fan

Inventor： Hsueh-Chung Chen ,  Chine-Gie Lou ,  Ping-Liang Liu ,  Su-Chen Fan

IPC: H01L23/48

CPC classification number: H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved interconnect structure and method of making such a device The improved interconnect electrically connects two otherwise separate areas on a semiconductor wafer. The interconnect preferably uses a copper conductor disposed within a trench and via structure formed in a low-k hybrid dielectric layer using a dual damascene process. Each contact region is served by a plurality of vias, each in communication with the trench conductor portion. The entry from the trench to the via is rounded for at least one and preferably all of the via structures.

Abstract translation: 改进的互连结构和制造这种器件的方法改进的互连电路连接半导体晶片上的另外两个分开的区域。 互连优选地使用布置在沟槽内的铜导体和使用双镶嵌工艺在低k混合电介质层中形成的通孔结构。 每个接触区域由多个通孔提供，每个通孔与沟槽导体部分连通。 从沟槽到通孔的入口对于至少一个并且优选地所有通孔结构是圆形的。

公开(公告)号：US20070020871A1

公开(公告)日：2007-01-25

申请号：US11174511

申请日：2005-07-06

Applicant: Hsueh-Chung Chen ,  Chine-Gie Lou ,  Su-Chen Fan

Inventor： Hsueh-Chung Chen ,  Chine-Gie Lou ,  Su-Chen Fan

IPC: H01L21/76

CPC classification number: H01L21/681

Abstract: Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.

Abstract translation: IC器件基板的对准方法。 第一IC器件衬底具有用于限定多个第一IC特征的第一前侧，与第一前侧相对的第一背面，以及形成在第一前侧或第一背面上的第一对准图案。 第二IC器件衬底具有用于限定多个第二IC特征的第二前侧，与第二前侧相对的第二后侧和形成在第二前侧或第二后侧上的第二对准图案。 应用第一光学检测器和第二光学检测器来检测第一和第二对准图案，以对准第一和第二IC器件基板。 具体地，第一和第二对准图案朝向相反方向的第一和第二光学检测器。

公开(公告)号：US07301239B2

公开(公告)日：2007-11-27

申请号：US10899252

申请日：2004-07-26

Applicant: Chien-Jung Wang ,  Su-Chen Fan ,  Ding-Da Hu ,  Hsueh-Chung Chen

Inventor： Chien-Jung Wang ,  Su-Chen Fan ,  Ding-Da Hu ,  Hsueh-Chung Chen

IPC: H01L29/41

CPC classification number: H01L22/34 ,  G01R31/2853 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wiring structure with improved resistance to void formation and a method of making the same are described. The wiring structure has a first conducting layer that includes a large area portion which is connected to an end of a protrusion with a plurality of “n” overlapping segments and at least one bending portion. The other end of the protrusion is connected to the bottom of a via which has an overlying second conducting layer. A bend is formed by overlapping the ends of two adjacent segments at an angle between 45° and 135°. The protrusion may also include at least one extension at a segment end beyond a bend. A bending portion and extension are used as bottlenecks to delay the diffusion of a vacancy from the large area portion to the vicinity of the via and is especially effective for copper interconnects or in a via test structure.

Abstract translation: 描述了具有改善的抗空隙形成的布线结构及其制造方法。 布线结构具有包括大面积部分的第一导电层，该区域部分连接到具有多个“n”个重叠部分和至少一个弯曲部分的突起的端部。 突起的另一端连接到具有覆盖的第二导电层的通路的底部。 通过以45°和135°之间的角度重叠两个相邻段的端部形成弯曲。 突出部还可以包括在弯曲部以外的段端部处的至少一个延伸部。 弯曲部分和延伸部用作延迟空位从大面积部分扩散到通孔附近的瓶颈，并且对于铜互连或通孔测试结构尤其有效。

公开(公告)号：US20060019414A1

公开(公告)日：2006-01-26

申请号：US10899252

申请日：2004-07-26

Applicant: Chien-Jung Wang ,  Su-Chen Fan ,  Ding-Da Hu ,  Hsueh-Chung Chen

Inventor： Chien-Jung Wang ,  Su-Chen Fan ,  Ding-Da Hu ,  Hsueh-Chung Chen

IPC: H01L21/66 ,  G01R31/26

CPC classification number: H01L22/34 ,  G01R31/2853 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wiring structure with improved resistance to void formation and a method of making the same are described. The wiring structure has a first conducting layer that includes a large area portion which is connected to an end of a protrusion with a plurality of “n” overlapping segments and at least one bending portion. The other end of the protrusion is connected to the bottom of a via which has an overlying second conducting layer. A bend is formed by overlapping the ends of two adjacent segments at an angle between 45° and 135°. The protrusion may also include at least one extension at a segment end beyond a bend. A bending portion and extension are used as bottlenecks to delay the diffusion of a vacancy from the large area portion to the vicinity of the via and is especially effective for copper interconnects or in a via test structure.

Abstract translation: 描述了具有改善的抗空隙形成的布线结构及其制造方法。 布线结构具有包括大面积部分的第一导电层，该区域部分连接到具有多个“n”个重叠部分和至少一个弯曲部分的突起的端部。 突起的另一端连接到具有覆盖的第二导电层的通路的底部。 通过以45°和135°之间的角度重叠两个相邻段的端部形成弯曲。 突出部还可以包括在弯曲部以外的段端部处的至少一个延伸部。 弯曲部分和延伸部用作延迟空位从大面积部分扩散到通孔附近的瓶颈，并且对于铜互连或通孔测试结构尤其有效。

公开(公告)号：US20070289467A1

公开(公告)日：2007-12-20

申请号：US11454577

申请日：2006-06-16

Applicant: Hsueh-Chung Chen ,  Ding-Chung Lu ,  Su-Chen Fan

Inventor： Hsueh-Chung Chen ,  Ding-Chung Lu ,  Su-Chen Fan

IPC: B41F1/18

CPC classification number: B41F1/18

Abstract: A direct printing lithography system for jet-printing a photoresist on a layer in the form of a desired circuit pattern is disclosed. The system includes a computer system for containing a programmed circuit pattern and generating printing signals and a jet printing head for receiving the printing signals from the computer system and printing the photoresist on the layer in the form of the programmed circuit pattern. A direct printing lithography method is also disclosed.

Abstract translation: 公开了一种用于以期望的电路图案形式在层上喷射印刷光致抗蚀剂的直接印刷光刻系统。 该系统包括用于容纳编程的电路图案和产生打印信号的计算机系统，以及用于从计算机系统接收打印信号并以编程的电路图案的形式在该层上打印光致抗蚀剂的喷墨打印头。 还公开了一种直接印刷光刻方法。

公开(公告)号：US20060099786A1

公开(公告)日：2006-05-11

申请号：US10971460

申请日：2004-10-22

Applicant: Su-Chen Fan ,  Hsueh-Chung Chen

Inventor： Su-Chen Fan ,  Hsueh-Chung Chen

IPC: H01L21/44

CPC classification number: H01L21/76825 ,  H01L21/76814

Abstract: A copper interconnect structure used in semiconductor devices includes surfaces having a surface roughness greater than 20 angstroms and which may be greater than 100 angstroms. The conformal surface of the copper interconnect structure confronts a surface roughened by ion bombardment. The copper interconnect structure is resistant to electromigration and stress migration failures.

Abstract translation: 用于半导体器件的铜互连结构包括具有大于20埃的表面粗糙度并且可以大于100埃的表面。 铜互连结构的共形表面面对通过离子轰击粗糙化的表面。 铜互连结构抵抗电迁移和应力迁移故障。

公开(公告)号：US20130320411A1

公开(公告)日：2013-12-05

申请号：US13488581

申请日：2012-06-05

Applicant: Su-Chen Fan ,  Balasubramanian S. Haran ,  David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

Inventor： Su-Chen Fan ,  Balasubramanian S. Haran ,  David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/66545

Abstract: A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel portion of the substrate. A metal oxide gate cap is present on an upper surface of the metal gate conductor. The metal oxide composition of the metal oxide gate cap may be zirconium oxide, aluminum oxide, magnesium oxide, hafnium oxide or a combination thereof. Contacts may extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region.