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公开(公告)号:US07838968B2
公开(公告)日:2010-11-23
申请号:US11293111
申请日:2005-12-05
申请人: Hongyong Zhang , Satoshi Teramoto
发明人: Hongyong Zhang , Satoshi Teramoto
CPC分类号: H01L21/31111 , G02F1/136227 , H01L21/02532 , H01L21/02675 , H01L21/2026 , H01L21/76801 , H01L21/76802 , H01L27/12 , H01L27/1248
摘要: There are disclosed TFTs having improved reliability. An interlayer dielectric film forming the TFTs is made of a silicon nitride film. Other interlayer dielectric films are also made of silicon nitride. The stresses inside the silicon nitride films forming these interlayer dielectric films are set between −5×109 and 5×109 dyn/cm2. This can suppress peeling of the interlayer dielectric films and difficulties in forming contact holes. Furthermore, release of hydrogen from the active layer can be suppressed. In this way, highly reliable TFTs can be obtained.
摘要翻译: 公开了具有提高的可靠性的TFT。 形成TFT的层间电介质膜由氮化硅膜构成。 其它层间绝缘膜也由氮化硅制成。 形成这些层间电介质膜的氮化硅膜内的应力设定在-5×109〜5×10 9 dyn / cm 2之间。 这可以抑制层间绝缘膜的剥离和形成接触孔的困难。 此外,可以抑制从活性层释放氢。 以这种方式,可以获得高度可靠的TFT。
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公开(公告)号:US07667817B2
公开(公告)日:2010-02-23
申请号:US11782042
申请日:2007-07-24
申请人: Hongyong Zhang , Satoshi Teramoto
发明人: Hongyong Zhang , Satoshi Teramoto
IPC分类号: G02F1/1339 , G02F1/1345
CPC分类号: G02F1/13392 , G02F1/1334 , G02F1/1339 , G02F1/1341 , G02F1/13454 , G02F2001/133388 , G09G3/3648
摘要: A laminated spacer portion formed by laminating various thin films that constitute thin-film transistors is disposed in peripheral driver circuits. As a result, even in a structure in which part of a sealing member is disposed above the peripheral driver circuits, pressure exerted from spacers in the sealing member is concentrated on the laminated spacer portion, whereby destruction of a thin-film transistor of the peripheral driver circuits can be prevented caused by the pressure from the sealing portion.
摘要翻译: 通过层叠各种构成薄膜晶体管的薄膜形成的层叠间隔部分设置在外围驱动电路中。 结果,即使在密封构件的一部分设置在外围驱动电路的上方的结构中,由密封构件中的间隔物施加的压力集中在层叠间隔部分上,从而破坏周边的薄膜晶体管 可以防止来自密封部的压力引起的驱动电路。
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公开(公告)号:US07646022B2
公开(公告)日:2010-01-12
申请号:US11382412
申请日:2006-05-09
申请人: Hongyong Zhang , Satoshi Teramoto
发明人: Hongyong Zhang , Satoshi Teramoto
IPC分类号: H01L27/14 , H01L29/04 , H01L29/15 , H01L31/036
CPC分类号: G02F1/136227 , G02F1/136209 , G02F1/136213
摘要: The present invention provides an active matrix type display device having a high aperture ratio and a required auxiliary capacitor. A source line and a gate line are overlapped with part of a pixel electrode. This overlapped region functions to be a black matrix. Further, an electrode pattern made of the same material as the pixel electrode is disposed to form the auxiliary capacitor by utilizing the pixel electrode. It allows a required value of auxiliary capacitor to be obtained without dropping the aperture ratio. Also, it allows the electrode pattern to function as a electrically shielding film for suppressing the cross-talk between the source and gate lines and the pixel electrode.
摘要翻译: 本发明提供一种具有高开口率的有源矩阵型显示装置和所需的辅助电容器。 源极线和栅极线与像素电极的一部分重叠。 该重叠区域用作黑矩阵。 此外,通过利用像素电极设置由与像素电极相同材料制成的电极图案以形成辅助电容器。 允许在不降低开口率的情况下获得所需的辅助电容值。 此外,它允许电极图案用作用于抑制源极和栅极线和像素电极之间的串扰的电屏蔽膜。
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公开(公告)号:US07602020B2
公开(公告)日:2009-10-13
申请号:US11522376
申请日:2006-09-18
IPC分类号: H01L27/12
CPC分类号: H01L27/12 , H01L27/124 , H01L29/458 , H01L29/4908 , H01L29/66757 , H01L29/78621 , H01L29/78696 , Y10S257/90
摘要: A thin film transistor device reduced substantially—in resistance between the source and the drain by incorporating a silicide film, which is fabricated by a process comprising forming a gate insulator film and a gate contact on a silicon substrate, anodically oxidizing the gate contact, covering an exposed surface of the silicon semiconductor with a metal, and irradiating an intense light such as a laser beam to the metal film either from the upper side or from an insulator substrate side to allow the metal coating to react with silicon to obtain a silicide film.
摘要翻译: 薄膜晶体管器件通过引入硅化物膜来降低源极和漏极之间的基本上的电阻,该硅化物膜通过包括在硅衬底上形成栅极绝缘膜和栅极接触的方法制造,阳极氧化栅极接触,覆盖 使用金属的硅半导体的暴露表面,并且从上侧或从绝缘体基板侧向金属膜照射强光如激光束,以允许金属涂层与硅反应以获得硅化物膜 。
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公开(公告)号:US20090072235A1
公开(公告)日:2009-03-19
申请号:US12241705
申请日:2008-09-30
IPC分类号: H01L29/04
CPC分类号: G02F1/1339 , G02F1/1345 , G02F1/13454 , G02F1/136277 , G09G3/3648 , G09G2320/0252
摘要: A display device of the present invention includes a first substrate and a second substrate opposed to each other, a liquid crystal interposed between the first substrate and the second substrate, an active matrix circuit and a driving circuit each comprising a thin film transistor formed over the first substrate, a resin layer formed over the active matrix circuit and the driving circuit, a spacer formed over the active matrix circuit, a sealing material formed over the driving circuit, and a filler included in the sealing material and in contact with the resin layer.
摘要翻译: 本发明的显示装置包括彼此相对的第一基板和第二基板,插入在第一基板和第二基板之间的液晶,有源矩阵电路和驱动电路,各自包括形成在第一基板和第二基板上的薄膜晶体管 第一基板,在有源矩阵电路和驱动电路上形成的树脂层,形成在有源矩阵电路上的间隔物,形成在驱动电路上的密封材料,以及包含在密封材料中并与树脂层接触的填料 。
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公开(公告)号:US20080020518A1
公开(公告)日:2008-01-24
申请号:US11782042
申请日:2007-07-24
申请人: Hongyong Zhang , Satoshi Teramoto
发明人: Hongyong Zhang , Satoshi Teramoto
IPC分类号: H01L21/71
CPC分类号: G02F1/13392 , G02F1/1334 , G02F1/1339 , G02F1/1341 , G02F1/13454 , G02F2001/133388 , G09G3/3648
摘要: A laminated spacer portion formed by laminating various thin films that constitute thin-film transistors is disposed in peripheral driver circuits. As a result, even in a structure in which part of a sealing member is disposed above the peripheral driver circuits, pressure exerted from spacers in the sealing member is concentrated on the laminated spacer portion, whereby destruction of a thin-film transistor of the peripheral driver circuits can be prevented caused by the pressure from the sealing portion.
摘要翻译: 通过层叠各种构成薄膜晶体管的薄膜形成的层叠间隔部分设置在外围驱动电路中。 结果,即使在密封构件的一部分设置在外围驱动电路的上方的结构中,由密封构件中的间隔物施加的压力集中在层叠间隔部分上,从而破坏周边的薄膜晶体管 可以防止来自密封部的压力引起的驱动电路。
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公开(公告)号:US20070085964A1
公开(公告)日:2007-04-19
申请号:US11538899
申请日:2006-10-05
IPC分类号: G02F1/1345
CPC分类号: G02F1/1339 , G02F1/1345 , G02F1/13454 , G02F1/136277 , G09G3/3648 , G09G2320/0252
摘要: A display device includes a pair of substrates sandwiching a liquid crystal with a thin film transistor formed over one of the pair of substrates and a sealing material formed between the pair of substrates for sealing the liquid crystal. The thin film transistor includes a semiconductor layer and a gate electrode between which is interposed a gate insulating film, an inorganic insulating film formed over at least the gate insulating film, an orientation film formed over the inorganic insulating film. The sealing material has a first region in contact with the orientation film and a second region in contact with the inorganic insulating film.
摘要翻译: 显示装置包括一对基板,其夹持液晶,该薄膜晶体管形成在所述一对基板中的一个基板上,并且形成在所述一对基板之间用于密封所述液晶的密封材料。 薄膜晶体管包括半导体层和栅极电极,其间插入有栅极绝缘膜,至少形成在栅极绝缘膜上的无机绝缘膜,形成在无机绝缘膜上的取向膜。 密封材料具有与取向膜接触的第一区域和与无机绝缘膜接触的第二区域。
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公开(公告)号:US20060189025A1
公开(公告)日:2006-08-24
申请号:US11381176
申请日:2006-05-02
申请人: Hongyong Zhang , Satoshi Teramoto
发明人: Hongyong Zhang , Satoshi Teramoto
IPC分类号: H01L21/00
CPC分类号: G02F1/13454 , G02F1/136204 , H01L27/0248 , H01L27/124 , H01L27/1255
摘要: To suppress the occurrence of a failure caused by static electricity in the manufacturing process of an active matrix type display device in which an active matrix circuit and peripheral drive circuits are integrated on a glass substrate, a protective capacitor to be connected to a short ring is formed using a semiconductor layer made from the same material as the active layer of a thin film transistor present under the short ring. This protective capacitor has a function to absorb an electric pulse generated in the plasma using process. Discharge patterns are provided to prevent an electric pulse from affecting each circuit.
摘要翻译: 为了抑制在有源矩阵电路和外围驱动电路集成在玻璃基板上的有源矩阵型显示装置的制造过程中由静电引起的故障,与短环连接的保护电容器 使用与存在于短环下的薄膜晶体管的有源层相同的材料制成的半导体层。 该保护电容器具有吸收等离子体使用过程中产生的电脉冲的功能。 提供放电模式以防止电脉冲影响每个电路。
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公开(公告)号:US07057677B2
公开(公告)日:2006-06-06
申请号:US10699796
申请日:2003-11-04
申请人: Hongyong Zhang , Satoshi Teramoto
发明人: Hongyong Zhang , Satoshi Teramoto
IPC分类号: G02F1/1333 , G02F1/1345
CPC分类号: G02F1/13454 , G02F1/136204 , H01L27/0248 , H01L27/124 , H01L27/1255
摘要: To suppress the occurrence of a failure caused by static electricity in the manufacturing process of an active matrix type display device in which an active matrix circuit and peripheral drive circuits are integrated on a glass substrate, a protective capacitor to be connected to a short ring is formed using a semiconductor layer made from the same material as the active layer of a thin film transistor present under the short ring. This protective capacitor has a function to absorb an electric pulse generated in the plasma using process. Discharge patterns are provided to prevent an electric pulse from affecting each circuit.
摘要翻译: 为了抑制在有源矩阵电路和外围驱动电路集成在玻璃基板上的有源矩阵型显示装置的制造过程中由静电引起的故障,与短环连接的保护电容器 使用与存在于短环下的薄膜晶体管的有源层相同的材料制成的半导体层。 该保护电容器具有吸收等离子体使用过程中产生的电脉冲的功能。 提供放电模式以防止电脉冲影响每个电路。
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公开(公告)号:US20050056849A1
公开(公告)日:2005-03-17
申请号:US10959981
申请日:2004-10-08
申请人: Hongyong Zhang , Satoshi Teramoto
发明人: Hongyong Zhang , Satoshi Teramoto
IPC分类号: G02F1/136 , G02F1/1362 , G02F1/1368 , H01L21/77 , H01L21/8238 , H01L21/84 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786 , H01L29/04
CPC分类号: H01L27/1214 , G02F1/13454 , H01L29/78618 , H01L29/78621
摘要: To provide a thin film transistor having a low OFF characteristic and to provide P-channel type and N-channel type thin film transistors where a difference in characteristics of the P-channel type and the N-channel type thin film transistors is corrected, a region 145 having a P-type behavior more potential than that of a drain region 146 is arranged between a channel forming region 134 and the drain region 146 in the P-channel type thin film transistor whereby the P-channel type thin film transistor having the low OFF characteristic can be provided and a low concentration impurity region 136 is arranged between a channel forming region 137 and a drain region 127 in the N-channel type thin film transistor whereby the N-channel type thin film transistor having the low OFF characteristic and where deterioration is restrained can be provided.
摘要翻译: 为了提供具有低OFF特性的薄膜晶体管,并且提供P沟道型和N沟道型薄膜晶体管,其中P沟道型和N沟道型薄膜晶体管的特性差被校正, 在P沟道型薄膜晶体管的沟道形成区域134和漏极区域146之间配置具有比漏极区域146更多的P型特性的区域145,由此P沟道型薄膜晶体管具有 可以提供低OFF特性,并且在N沟道型薄膜晶体管中的沟道形成区域137和漏极区域127之间布置低浓度杂质区域136,由此具有低OFF特性的N沟道型薄膜晶体管和 可以抑制劣化。
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