公开(公告)号：US07096345B1

公开(公告)日：2006-08-22

申请号：US10672774

申请日：2003-09-26

申请人： Hong-Yi Hubert Chen ,  Richard Yen-Ching Lee ,  Geoffrey Yung ,  Jensen Tjeng

发明人： Hong-Yi Hubert Chen ,  Richard Yen-Ching Lee ,  Geoffrey Yung ,  Jensen Tjeng

IPC分类号： G06F9/30

CPC分类号： G06F9/3838 ,  G06F9/3828 ,  G06F9/3855 ,  G06F9/3857

摘要： A data processing system for executing a plurality of instructions having a prescribed program order comprises a register file, a reorder buffer, and a plurality of functional units. The register file includes a plurality of registers to store data. The reorder buffer includes N buffer locations of which M buffer locations are bypassable and N−M buffer locations are non-bypassable, wherein N and M are integers and N>M. Each functional unit is capable of executing instructions regardless of the prescribed program order. The reorder buffer temporarily stores data corresponding to the plurality of instructions. When data of one of the plurality of instructions to be executed by a corresponding one of the plurality of functions units is temporarily stored in one of the M bypassable buffer locations, the reorder buffer transfers the data in one of the bypassable M buffer locations to the corresponding one of the functional units in order to execute the instruction. The register file also stores data corresponding to retired ones of the plurality of instructions.

摘要翻译： 用于执行具有规定程序顺序的多个指令的数据处理系统包括寄存器文件，重新排序缓冲器和多个功能单元。 寄存器文件包括多个用于存储数据的寄存器。 重排序缓冲器包括N个缓冲器位置，其中M个缓冲器位置可旁路，N-M个缓冲器位置是不可旁路的，其中N和M是整数，N> M。 每个功能单元能够执行指令，而不管规定的程序顺序如何。 重新排序缓冲器临时存储与多条指令相对应的数据。 当要由多个功能单元中的相应一个功能单元执行的多个指令中的一个指令的数据被临时存储在M个可旁路缓冲器单元之一中时，重新排序缓冲器将一个可旁路M缓冲器位置中的数据传送到 相应的一个功能单元，以便执行该指令。 寄存器文件还存储与多个指令中的退出的指令相对应的数据。

公开(公告)号：US06816943B2

公开(公告)日：2004-11-09

申请号：US10429746

申请日：2003-05-06

申请人： Hong-Yi Hubert Chen

发明人： Hong-Yi Hubert Chen

IPC分类号： G06F1200

CPC分类号： G06F9/3808 ,  G06F9/3802 ,  G06F12/0848 ,  G06F12/0897

摘要： A processing system is disclosed. The processing system includes at least one cache and at least one scratch pad memory. The system also includes a processor for accessing the at least one cache and at least one scratch pad memory. The at least one scratch pad memory is smaller in size than the at least one cache. The processor accesses the data in the at least one scratch pad memory before accessing the at least one cache to determine if the appropriate data is therein. There are two important features of the present invention. The first feature is that an instruction can be utilized to fill a scratch pad memory with the appropriate data in an efficient manner. The second feature is that once the scratch pad has the appropriate data, it can be accessed more efficiently to retrieve this data within the cache and memory space not needed for this data. This has a particular advantage for frequently used routines, such as a mathematical algorithm to minimize the amount of space utilized in the cache for such routines. Accordingly, the complexity of the cache is not required using the scratch pad memory as well as space within the cache is not utilized.

摘要翻译： 公开了一种处理系统。 处理系统包括至少一个缓存和至少一个临时存储器。 该系统还包括用于访问至少一个高速缓存和至少一个临时存储器的处理器。 所述至少一个临时存储器的尺寸小于所述至少一个高速缓存。 在访问至少一个高速缓存之前，处理器访问至少一个临时存储器中的数据，以确定其中是否存在适当的数据。 本发明有两个重要特征。 第一个特征是可以利用指令以有效的方式用适当的数据填充暂存器存储器。 第二个特征是，一旦便笺簿具有适当的数据，可以更有效地访问它，以便在该数据不需要的高速缓存和存储器空间内检索该数据。 这对于经常使用的例程具有特别的优点，例如最小化用于这种例程的高速缓存中使用的空间量的数学算法。 因此，不需要使用便笺式存储器来实现高速缓存的复杂性，并且不利用高速缓存内的空间。

公开(公告)号：US06643736B1

公开(公告)日：2003-11-04

申请号：US09650244

申请日：2000-08-29

申请人： Hong-Yi Hubert Chen

发明人： Hong-Yi Hubert Chen

IPC分类号： G06F1208

CPC分类号： G06F9/3808 ,  G06F9/3802 ,  G06F12/0848 ,  G06F12/0897

摘要： A processing system is disclosed. The processing system includes at least one cache and at least one scratch pad memory. The system also includes a processor for accessing the at least one cache and at least one scratch pad memory. The at least one scratch pad memory is smaller in size than the at least one cache. The processor accesses the data in the at least one scratch pad memory before accessing the at least one cache to determine if the appropriate data is therein. There are two important features of the present invention. The first feature is that an instruction can be utilized to fill a scratch pad memory with the appropriate data in an efficient manner. The second feature is that once the scratch pad has the appropriate data, it can be accessed more efficiently to retrieve this data within the cache and memory space not needed for this data. This has a particular advantage for frequently used routines, such as a mathematical algorithm to minimize the amount of space utilized in the cache for such routines. Accordingly, the complexity of the cache is not required using the scratch pad memory as well as space within the cache is not utilized.

摘要翻译： 公开了一种处理系统。 处理系统包括至少一个缓存和至少一个临时存储器。 该系统还包括用于访问至少一个高速缓存和至少一个临时存储器的处理器。 所述至少一个临时存储器的尺寸小于所述至少一个高速缓存。 在访问至少一个高速缓存之前，处理器访问至少一个临时存储器中的数据，以确定其中是否存在适当的数据。 本发明有两个重要特征。 第一个特征是可以利用指令以有效的方式用适当的数据填充暂存器存储器。 第二个特征是，一旦便笺簿具有适当的数据，可以更有效地访问它，以便在该数据不需要的高速缓存和存储器空间内检索该数据。 这对于经常使用的例程具有特别的优点，例如最小化用于这种例程的高速缓存中使用的空间量的数学算法。 因此，不需要使用便笺式存储器来实现高速缓存的复杂性，并且不利用高速缓存内的空间。

公开(公告)号：US06473864B1

公开(公告)日：2002-10-29

申请号：US09364621

申请日：1999-07-29

申请人： Hong-Yi Hubert Chen

发明人： Hong-Yi Hubert Chen

IPC分类号： G06F126

CPC分类号： G06F9/3814 ,  G06F1/3203 ,  G06F1/329 ,  G06F8/4432 ,  G06F9/32 ,  G06F9/3802 ,  Y02D10/24 ,  Y02D10/41

摘要： A method and system for controlling a program in a processor system is disclosed. The processor system includes processor, a normal memory and a fast memory. The method and system comprises partitioning the program into a performance critical portion and a non-critical portion; and storing the performance critical portion of the program into the fast memory. The method and system further includes storing the non-critical portion in the normal memory, and causing the processor to execute the performance critical portion and non-critical portions at the appropriate time. Accordingly, through the use of the present invention power is conserved in the processing system when executing a program.

摘要翻译： 公开了一种用于控制处理器系统中的程序的方法和系统。 处理器系统包括处理器，正常存储器和快速存储器。 该方法和系统包括将程序划分为性能关键部分和非关键部分; 并将程序的性能关键部分存储到快速存储器中。 该方法和系统还包括将非关键部分存储在正常存储器中，并且使得处理器在适当的时间执行性能关键部分和非关键部分。 因此，通过使用本发明，在执行程序时在处理系统中节省功率。

公开(公告)号：US07882332B1

公开(公告)日：2011-02-01

申请号：US12287782

申请日：2008-10-13

申请人： Hong-Yi Hubert Chen ,  Henry Hin Kwong Fan

发明人： Hong-Yi Hubert Chen ,  Henry Hin Kwong Fan

IPC分类号： G06F9/34

CPC分类号： G06F12/0292 ,  G06F9/30098 ,  G06F9/30138 ,  G06F9/30189 ,  G06F9/3857

摘要： A register system for a data processing system includes an address encoder that generates an encoded address based on a processor mode identifier and a register identifier and memory comprising 2T−1 unbanked registers. The encoded address identifies one of the 2T−1 unbanked registers associated with one of the P processor modes. The encoded address comprises T bits. The register identifier identifies one of 2T−1 unbanked registers. The processor mode identifier identifies P processor modes, where T and P are integers greater than two.

摘要翻译： 用于数据处理系统的寄存器系统包括地址编码器，其基于处理器模式标识符和寄存器标识符生成编码地址，并且存储器包括2T-1无库存寄存器。 编码地址标识与P处理器模式之一相关联的2T-1未分组寄存器之一。 编码地址包括T位。 寄存器标识符标识2T-1无库存寄存器之一。 处理器模式标识符识别P处理器模式，其中T和P是大于2的整数。

公开(公告)号：US06356995B2

公开(公告)日：2002-03-12

申请号：US09109762

申请日：1998-07-02

申请人： Hong-Yi Hubert Chen

发明人： Hong-Yi Hubert Chen

IPC分类号： G06F9455

CPC分类号： G06F9/3017 ,  G06F9/30145

摘要： A processing system in accordance with the present invention is disclosed. The processing system comprises a processor and a microcode sequencer coupled to the processor. The microcode sequencer includes a plurality of modules. Each of the modules enables a specific function based upon a selection signal from the processor. A system and method in accordance with the present invention provides for many advantages over conventional systems. First of all, there is an efficient register bank and the hardware is smaller and more efficient than a DSP. Finally, since it is possible to program macro instructions for different applications, it is more flexible than DSP systems. It also is smaller, has a lower gate count and is faster to market because it is software programmable. Unlike RISC or coprocessor type systems, only a single assembler is needed to handle DSP and multimedia instructions. In addition, a large cache memory is not required while having a higher code density for a particular application. Finally, it requires a smaller register file through the general purpose processor than a media processor, and thus context switching is faster. It does not have a big data path as a media processor. It also has higher code density and it is easier to program than a media processor application. Accordingly, a system and method in accordance with the present invention provides significant utility over existing conventional systems.

摘要翻译： 公开了根据本发明的处理系统。 处理系统包括耦合到处理器的处理器和微码序列器。 微码排序器包括多个模块。 每个模块基于来自处理器的选择信号实现特定功能。 根据本发明的系统和方法提供了与常规系统相比的许多优点。 首先，有一个高效的注册库，硬件比DSP更小，更高效。 最后，由于可以为不同的应用编程宏指令，所以它比DSP系统更灵活。 它也更小，门数更少，市场更快，因为它是软件可编程的。 与RISC或协处理器类型系统不同，只需要一个汇编器来处理DSP和多媒体指令。 另外，在特定应用程序具有较高代码密度的情况下，不需要大型高速缓冲存储器。最后，与通常的处理器相比，它需要比介质处理器更小的寄存器文件，因此上下文切换更快。 它没有作为媒体处理器的大数据路径。 它还具有更高的代码密度，并且比媒体处理器应用程序更容易编程。 因此，根据本发明的系统和方法提供了超过现有常规系统的显着效用。