公开(公告)号：US06887512B2

公开(公告)日：2005-05-03

申请号：US10214727

申请日：2002-08-09

申请人： Hisashi Wakako ,  Masahiro Iba ,  Kazuhisa Sato ,  Kazuo Kimura

发明人： Hisashi Wakako ,  Masahiro Iba ,  Kazuhisa Sato ,  Kazuo Kimura

IPC分类号： H05K3/34 ,  H01L23/12 ,  H01L23/498 ,  H05K3/24 ,  B05D5/12

CPC分类号： H05K3/244 ,  H01L23/49811 ,  H01L2924/0002 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49156 ,  H01L2924/00

摘要： A method for fabricating a component board which includes forming a first main-face-side Au plating layer on surfaces of main-face-side connection terminals and a first back-face-side Au plating layer on surfaces of back-face-side connection terminals of the component board; covering the first main-face-side Au plating layer with a protection layer; forming a second back-face-side Au plating layer on the first back-face-side Au plating layer; and removing the protection layer after completing the second Au plating step. Alternatively, the first back-face-side Au plating layer may be removed after completing the masking step. Displacement Au plating is used as the first and second Au plating.

摘要翻译： 一种部件板的制造方法，其包括在背面侧连接面的主面侧连接端子和第一背面侧Au镀层的表面上形成第一主面侧Au镀层 组件板端子; 用保护层覆盖第一主面Au镀层; 在所述第一背面侧Au镀层上形成第二背面侧Au镀层; 以及在完成第二Au镀层步骤之后去除保护层。 或者，可以在完成掩模步骤之后去除第一背面侧Au镀层。 使用位移Au电镀作为第一和第二Au镀层。

公开(公告)号：US06472609B2

公开(公告)日：2002-10-29

申请号：US09866999

申请日：2001-05-25

申请人： Hisashi Wakako ,  Masahiro Iba ,  Kazuhisa Sato ,  Kazuo Kimura

发明人： Hisashi Wakako ,  Masahiro Iba ,  Kazuhisa Sato ,  Kazuo Kimura

IPC分类号： H05K103

CPC分类号： H05K3/244 ,  H01L23/49811 ,  H01L2924/0002 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49156 ,  H01L2924/00

摘要： A printed-wiring substrate 1 has main-face-side connection terminals 33 for solder-bonding to connection terminals 83 of an IC chip 81 on a main face 1A thereof and back-face-side connection terminals 41 for connecting, through mechanical contact, to connection terminals 93 of a motherboard 91 on a back face 1B thereof. The surface of each of the main-face-side connection terminals 33 is covered with a main-face-side displacement Au plating layer 45 having a thickness of 0.03 to 0.12 &mgr;m, and the surface of each of the back-face-side connection terminals 41 is covered with a back-face-side displacement Au plating layer 55, which is thicker than the main-face-side displacement Au plating layer 45 and has a thickness of 0.2 &mgr;m or greater.

摘要翻译： 印刷布线基板1具有用于焊接到其主面1A上的IC芯片81的连接端子83的主面侧连接端子33和用于通过机械接触连接的背面侧连接端子41， 连接到母板91的背面1B上的连接端子93。 每个主面侧连接端子33的表面被厚度为0.03至0.12μm的主面侧位移Au镀层45覆盖，并且每个背面侧连接 端子41覆盖有比主面侧位移Au镀层45厚的厚度为0.2μm以上的背面侧位移Au镀层55。

公开(公告)号：US06546622B2

公开(公告)日：2003-04-15

申请号：US09808980

申请日：2001-03-16

申请人： Masahiro Iba ,  Hisashi Wakako ,  Kazuhisa Sato ,  Haruhiko Murata ,  Kazuyuki Takahashi ,  Kenzo Kawaguchi

发明人： Masahiro Iba ,  Hisashi Wakako ,  Kazuhisa Sato ,  Haruhiko Murata ,  Kazuyuki Takahashi ,  Kenzo Kawaguchi

IPC分类号： H05K302

CPC分类号： H01L23/5383 ,  H01L2224/16225 ,  H05K1/0266 ,  H05K3/28 ,  H05K3/381 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2203/107 ,  H05K2203/122 ,  H05K2203/161 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158

摘要： A printed-wiring substrate 1 includes internal dielectric resin layers 12 and 14. A main-surface-side external dielectric resin layer 13 is formed on the internal dielectric resin layer 12 such that the surface thereof serves as a substrate main-surface 1A. A back-surface-side external dielectric resin layer 15 is formed on the internal dielectric resin layer 14 such that the surface thereof serves as a substrate back-surface 1B. A surface 12A of the main-surface-side internal dielectric resin layer 12 and a surface 14A of the back-surface-side internal dielectric resin layer 14 are roughened. The substrate main-surface 1A and the substrate back-surface 1B are roughened such that surface roughness thereof is lower than that of the surfaces 12A and 14A.

摘要翻译： 印刷布线基板1包括内部电介质树脂层12和14.主表面侧外部电介质树脂层13形成在内部电介质树脂层12上，使得其表面用作基板主表面1A。 在内部电介质树脂层14上形成背面侧外部电介质树脂层15，使其表面作为基板背面1B。 主表面侧内部电介质树脂层12的表面12A和背面侧内部电介质树脂层14的表面14A被粗糙化。 基板主表面1A和基板背面1B被粗糙化，使得表面粗糙度低于表面12A和14A的表面粗糙度。

公开(公告)号：US06495211B2

公开(公告)日：2002-12-17

申请号：US09882016

申请日：2001-06-18

申请人： Masahiro Iba ,  Hisashi Wakako ,  Kazuhisa Sato ,  Hiroyuki Hashimoto ,  Yasuo Doi

发明人： Masahiro Iba ,  Hisashi Wakako ,  Kazuhisa Sato ,  Hiroyuki Hashimoto ,  Yasuo Doi

IPC分类号： B05D310

CPC分类号： H05K3/187 ,  H01L21/288 ,  H01L21/67028 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K3/244 ,  H01L2924/00

摘要： A process for producing a substrate 1 having a base-metal plating layer, which includes an immersion step for immersing the substrate 1 in a plating solution contained in a plating tank 33, to thereby form a base-metal plating layer; a washing step for removing the substrate 1 from the plating tank 33, transferring the substrate 1 to a washing tank, and washing the substrate 1; and a cooling step for applying a cooling liquid to the substrate 1 during at least a portion of the period during which the substrate is transferred to a position where the washing step is carried out after completing the immersion step, to thereby cool the substrate 1. An apparatus for carrying out the above process is also disclosed.

摘要翻译： 一种具有基底金属镀层的基板1的制造方法，其包括将基板1浸渍在镀槽33中所含的镀液中的浸渍工序，从而形成基底金属镀层; 洗涤步骤，用于从电镀槽33去除衬底1，将衬底1转移到洗涤槽中，并洗涤衬底1; 以及在完成浸渍步骤之后将衬底转移到进行洗涤步骤的位置的至少一部分时间内将冷却液施加到衬底1从而冷却衬底1的冷却步骤。 还公开了一种用于执行上述过程的装置。

公开(公告)号：US07488896B2

公开(公告)日：2009-02-10

申请号：US11265952

申请日：2005-11-03

申请人： Hajime Saiki ,  Masahiro Iba

发明人： Hajime Saiki ,  Masahiro Iba

IPC分类号： H05K1/16

CPC分类号： H05K3/3436 ,  H01L23/49816 ,  H01L2224/81191 ,  H01L2924/01322 ,  H05K3/3452 ,  H05K3/3463 ,  H05K2201/09427 ,  H05K2201/099 ,  H05K2201/10992 ,  H05K2203/0465 ,  H05K2203/0594 ,  Y02P70/613 ,  H01L2924/00

摘要： An electronic device comprised of a wiring board with a semiconductor component. The device is unlikely to have any defects, such as cracks to a solder joint portion during a reflow process of a flip-chip connection. The semiconductor component is flip-chip bonded at a pad array at a component side thereof to a pad array at a board side by way of an individual solder joint portion. In a solder resist layer at a semiconductor component side and a solder resist layer at a board side, D/D0 is prepared to be in a range of 0.70 to 0.99, where D is a bottom inner diameter of an opening at the board side and D0 is a bottom inner diameter of an opening at the component side.

摘要翻译： 一种由具有半导体部件的布线板构成的电子装置。 在倒装芯片连接的回流工艺期间，器件不太可能具有任何缺陷，例如焊接部分的裂纹。 半导体部件在其一侧的焊盘阵列处通过单独的焊接部分在基板侧被倒装成焊盘阵列。 在半导体部件侧的阻焊层和基板侧的阻焊层中，D / D0为0.70〜0.99的范围，D为板侧的开口的底部内径， D0是部件侧的开口的底部内径。

公开(公告)号：US06998336B1

公开(公告)日：2006-02-14

申请号：US11070200

申请日：2005-03-03

申请人： Masahiro Iba ,  Hajime Sakai ,  Takahiro Hayashi

发明人： Masahiro Iba ,  Hajime Sakai ,  Takahiro Hayashi

IPC分类号： H01L21/44

CPC分类号： H05K3/3484 ,  H05K3/244 ,  H05K3/3463 ,  H05K3/3473 ,  H05K2203/043

摘要： A method of producing a wiring board includes a preliminary plating step of forming a solder resist layer such that the main layer of each metal pad of the board is exposed in each corresponding opening and covering the surface of the exposed main layer with a preliminary Sn plated layer. A solder paste application step involves applying a solder paste, containing solder powder comprised of the high temperature Sn solder and thicker than the preliminary Sn plated layer, on the preliminary Sn plated layer. A subsequent solder melting step involves forming the Sn solder covering layer by melting the solder paste layer together with the preliminary Sn plated layer by heating the solder paste layer to a temperature higher than the liquid phase line temperature of the high temperature Sn solder. This wettingly extends the melted layers over the surface of the main layer.

摘要翻译： 一种布线基板的制造方法，其特征在于，具有：形成阻焊层的预镀工序，使得板的每个金属焊盘的主层在相应的开口中露出，并且利用预镀Sn镀层覆盖暴露的主层的表面 层。 焊膏施加步骤包括在预镀Sn镀层上涂覆含有由高温Sn焊料构成的焊料粉末并且比预备Sn镀层厚的焊膏。 随后的焊料熔化步骤包括通过将焊膏层加热到高于高温Sn焊料的液相管线温度的温度，通过将焊膏层与预浸镀锡层一起熔化来形成Sn焊料覆盖层。 这使熔融层在主层的表面上湿润地延伸。