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8 条记录 (耗时 0.019 秒)

    D/A CONVERTER
    1.
    发明申请
    D/A CONVERTER 失效
    D / A转换器

    公开(公告)号：US20080224909A1

    公开(公告)日：2008-09-18

    申请号：US12048309

    申请日：2008-03-14

    申请人： Shogo Itoh ,  Hisao Suzuki

    发明人： Shogo Itoh ,  Hisao Suzuki

    IPC分类号： H03M1/66

    CPC分类号： H03M1/0863 ,  H03M1/765

    摘要： A digital-analog converter including a first selection circuit of switch elements, which are coupled to each other and to a high potential power supply, and a second selection circuit of switch elements, which are coupled to each other and to a low potential power supply. First and second voltage dividing circuit each include series-connected resistor elements, each coupled between adjacent switch elements of the corresponding selection circuit. A control circuit provides a control signal to the selection circuits to activate one of the switch elements in each selection circuit and couple the activated switch element to the corresponding potential power supply. The first and second voltage dividing circuits divide voltages of the high and low potential power supplies with the resistor elements between the activated switch elements.

    摘要翻译： 一种数模转换器，包括彼此耦合并且连接到高电位电源的开关元件的第一选择电路和开关元件的第二选择电路，它们彼此耦合并且连接到低电位电源 。 第一和第二分压电路各自包括串联连接的电阻器元件，每个电阻元件耦合在相应选择电路的相邻开关元件之间。 控制电路向选择电路提供控制信号以激活每个选择电路中的一个开关元件，并将激活的开关元件耦合到相应的电位电源。 第一和第二分压电路将高电位和低电位电源的电压与激活的开关元件之间的电阻元件分开。

    D/A converter
    2.
    发明授权
    D/A converter 失效
    D / A转换器

    公开(公告)号：US07652606B2

    公开(公告)日：2010-01-26

    申请号：US12048309

    申请日：2008-03-14

    申请人： Shogo Itoh ,  Hisao Suzuki

    发明人： Shogo Itoh ,  Hisao Suzuki

    IPC分类号： H03M1/66

    CPC分类号： H03M1/0863 ,  H03M1/765

    摘要： A digital-analog converter including a first selection circuit of switch elements, which are coupled to each other and to a high potential power supply, and a second selection circuit of switch elements, which are coupled to each other and to a low potential power supply. First and second voltage dividing circuit each include series-connected resistor elements, each coupled between adjacent switch elements of the corresponding selection circuit. A control circuit provides a control signal to the selection circuits to activate one of the switch elements in each selection circuit and couple the activated switch element to the corresponding potential power supply. The first and second voltage dividing circuits divide voltages of the high and low potential power supplies with the resistor elements between the activated switch elements.

    摘要翻译： 一种数模转换器，包括彼此耦合并且连接到高电位电源的开关元件的第一选择电路和开关元件的第二选择电路，它们彼此耦合并且连接到低电位电源 。 第一和第二分压电路各自包括串联连接的电阻器元件，每个电阻元件耦合在相应选择电路的相邻开关元件之间。 控制电路向选择电路提供控制信号以激活每个选择电路中的一个开关元件，并将激活的开关元件耦合到相应的电位电源。 第一和第二分压电路将高电位和低电位电源的电压与激活的开关元件之间的电阻元件分开。

    A/D converter circuit and current supply circuit
    3.
    发明授权
    A/D converter circuit and current supply circuit 有权
    A / D转换电路和电流源电路

    公开(公告)号：US06788239B2

    公开(公告)日：2004-09-07

    申请号：US10426636

    申请日：2003-05-01

    申请人： Hisao Suzuki ,  Shogo Itoh

    发明人： Hisao Suzuki ,  Shogo Itoh

    IPC分类号： H03M136

    CPC分类号： H03M1/0604 ,  H03M1/002 ,  H03M1/36

    摘要： It is intended to provide an A/D converter circuit with which, by using a clock signal, on the basis of an analog voltage inputted a predetermined time past, it is possible to select suitably comparators to be operated and comparators to be rested, and which has small consumed power. A parallel-type A/D-converter circuit 200 converts an analog voltage VIN to a digital value DOUT at intervals of a predetermined period by means of a clock signal CLK using chopper-type comparators 1-7. The comparators 1-7 can each be set by first and second setting signals CONT1A etc. to either of an operating state and a resting state. A comparator control circuit section 211 performs logical processing on the comparator outputs OUT1-OUT7 in the preceding conversion to generate the first and second setting signals CONT1A etc., and brings some of the comparators to the operating state and holds the remaining comparators in the resting state.

    摘要翻译： 旨在提供一种A / D转换器电路，通过使用时钟信号，通过输入预定时间过去的模拟电压，可以选择要被操作的适当的比较器和待休止的比较器，以及 功耗小。 并行型A / D转换器电路200通过使用斩波型比较器1-7的时钟信号CLK将模拟电压VIN以预定周期的间隔转换为数字值DOUT。 比较器1-7可以由第一和第二设置信号CONT1A等设置为操作状态和静止状态中的任一个。 比较器控制电路部分211在前一转换中对比较器输出端OUT1-OUT7执行逻辑处理，以产生第一和第二设置信号CONT1A等，并使一些比较器进入运行状态并将其余的比较器保持在休眠状态 州。

    A/D converter circuit and current supply circuit
    4.
    发明申请
    A/D converter circuit and current supply circuit 有权
    A / D转换电路和电流源电路

    公开(公告)号：US20050052308A1

    公开(公告)日：2005-03-10

    申请号：US10890412

    申请日：2004-07-14

    申请人： Hisao Suzuki ,  Shogo Itoh

    发明人： Hisao Suzuki ,  Shogo Itoh

    IPC分类号： H03M1/00 ,  H03M1/36

    CPC分类号： H03M1/0604 ,  H03M1/002 ,  H03M1/36

    摘要： It is intended to provide an A/D converter circuit with which, by using a clock signal, on the basis of an analog voltage inputted a predetermined time past, it is possible to select suitably comparators to be operated and comparators to be rested, and which has small consumed power. A parallel-type A/D-converter circuit 200 converts an analog voltage VIN to a digital value DOUT at intervals of a predetermined period by means of a clock signal CLK using chopper-type comparators 1-7. The comparators 1-7 can each be set by first and second setting signals CONT1A etc. to either of an operating state and a resting state. A comparator control circuit section 211 performs logical processing on the comparator outputs OUT1-OUT7 in the preceding conversion to generate the first and second setting signals CONTLA etc., and brings some of the comparators to the operating state and holds the remaining comparators in the resting state.

    摘要翻译： 旨在提供一种A / D转换器电路，通过使用时钟信号，通过输入预定时间过去的模拟电压，可以选择要被操作的适当的比较器和待休止的比较器，以及 功耗小。 并行型A / D转换器电路200通过使用斩波型比较器1-7的时钟信号CLK将模拟电压VIN以预定周期的间隔转换为数字值DOUT。 比较器1-7可以由第一和第二设置信号CONT1A等设置为操作状态和静止状态中的任一个。 比较器控制电路部分211在前一转换中对比较器输出端OUT1-OUT7执行逻辑处理，以产生第一和第二设置信号CONTLA等，并使一些比较器进入运行状态并将剩余的比较器保持在休眠状态 州。

    Operational amplifier
    5.
    发明授权
    Operational amplifier 有权
    运算放大器

    公开(公告)号：US08310306B2

    公开(公告)日：2012-11-13

    申请号：US12796500

    申请日：2010-06-08

    申请人： Shogo Itoh ,  Hisao Suzuki

    发明人： Shogo Itoh ,  Hisao Suzuki

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45183 ,  H03F3/3022 ,  H03F3/45179 ,  H03F2203/45646 ,  H03F2203/45652

    摘要： An operational amplifier includes a first amplifier to which an input signal is applied, and a second amplifier to which an output of the first amplifier is applied, wherein the second amplifier includes a first transistor including a gate to which the output of the first amplifier is applied, and a second transistor including a gate to which the output of the first amplifier is applied, and a drain coupled to a source of the first transistor.

    摘要翻译： 运算放大器包括施加输入信号的第一放大器和施加第一放大器的输出的第二放大器，其中第二放大器包括第一晶体管，第一晶体管包括第一放大器的输出为第 以及包括施加了第一放大器的输出的栅极的第二晶体管和耦合到第一晶体管的源极的漏极。

    Current supply circuit
    6.
    发明授权
    Current supply circuit 有权
    电流供应电路

    公开(公告)号：US06985095B2

    公开(公告)日：2006-01-10

    申请号：US10890412

    申请日：2004-07-14

    申请人： Hisao Suzuki ,  Shogo Itoh

    发明人： Hisao Suzuki ,  Shogo Itoh

    IPC分类号： H03M1/36 ,  G05F1/10

    CPC分类号： H03M1/0604 ,  H03M1/002 ,  H03M1/36

    摘要： It is intended to provide an A/D converter circuit with which, by using a clock signal, on the basis of an analog voltage inputted a predetermined time past, it is possible to select suitably comparators to be operated and comparators to be rested, and which has small consumed power. A parallel-type A/D-converter circuit 200 converts an analog voltage VIN to a digital value DOUT at intervals of a predetermined period by means of a clock signal CLK using chopper-type comparators 1–7. The comparators 1–7 can each be set by first and second setting signals CONT1A etc. to either of an operating state and a resting state. A comparator control circuit section 211 performs logical processing on the comparator outputs OUT1–OUT7 in the preceding conversion to generate the first and second setting signals CONT1A etc., and brings some of the comparators to the operating state and holds the remaining comparators in the resting state.

    摘要翻译： 旨在提供一种A / D转换器电路，通过使用时钟信号，通过输入预定时间过去的模拟电压，可以选择要被操作的适当的比较器和待休止的比较器，以及 功耗小。 并行型A / D转换器电路200通过使用斩波型比较器1-7的时钟信号CLK将模拟电压VIN以预定周期的间隔转换为数字值DOUT。 比较器1-7可以通过第一和第二设置信号CONT 1A等设置为操作状态和静止状态中的任一个。 比较器控制电路部分211在前一转换中对比较器输出端OUT 1 -OUT 7执行逻辑处理，以产生第一和第二设置信号CONT 1A等，并使一些比较器保持在运行状态并保持其余的 比较者处于休息状态。