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公开(公告)号：US10482013B2
公开(公告)日：2019-11-19
申请号：US15513407
申请日：2014-09-30
发明人： Charles S. Johnson , Harumi Kuno , Goetz Graefe , Haris Volos , Mark Lillibridge , James Hyungsun Park , Wey Guy
IPC分类号： G06F12/0804 , G06F12/0868 , G06F12/12 , G06F11/14
摘要： Systems and methods associated with page modification are disclosed. One example method may be embodied on a non-transitory computer-readable medium storing computer-executable instructions. The instructions, when executed by a computer, may cause the computer to fetch a page to a buffer pool in a memory. The page may be fetched from at least one of a log and a backup using single page recovery. The instructions may also cause the computer to store a modification of the page to the log. The modification may be stored to the log as a log entry. The instructions may also cause the computer to evict the page from memory when the page is replaced in the buffer pool. Page writes associated with the eviction may be elided.
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公开(公告)号：US10416931B2
公开(公告)日：2019-09-17
申请号：US15283211
申请日：2016-09-30
发明人： Pradeep Fernando , Mijung Kim , Haris Volos , Jun Li
摘要： Examples herein involve fault tolerance in a shared memory. In examples herein, a metadata store of a shared memory indicating versions of data partitions of a resilient distributed dataset and a valid flag for the partitions of the resilient distributed dataset are used to achieve fault tolerance and/or recover from faults in the share memory.
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公开(公告)号：US20170300412A1
公开(公告)日：2017-10-19
申请号：US15513407
申请日：2014-09-30
发明人： Charles S. Johnson , Harumi Kuno , Goetz Graefe , Haris Volos , Mark Lillibridge , James Hyungsun Park , Wey Guy
CPC分类号： G06F12/0804 , G06F11/1446 , G06F11/1474 , G06F12/0868 , G06F12/12 , G06F2201/80 , G06F2212/1016
摘要： Systems and methods associated with page modification are disclosed. One example method may be embodied on a non-transitory computer-readable medium storing computer-executable instructions. The instructions, when executed by a computer, may cause the computer to fetch a page to a buffer pool in a memory. The page may be fetched from at least one of a log and a backup using single page recovery. The instructions may also cause the computer to store a modification of the page to the log. The modification may be stored to the log as a log entry. The instructions may also cause the computer to evict the page from memory when the page is replaced in the buffer pool. Page writes associated with the eviction may be elided.
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公开(公告)号：US10372602B2
公开(公告)日：2019-08-06
申请号：US15545901
申请日：2015-01-30
发明人： Sanketh Nalli , Haris Volos , Kimberly Keeton
IPC分类号： G06F12/02 , G06F12/0804 , G06F12/0868
摘要： Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.
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公开(公告)号：US20180018258A1
公开(公告)日：2018-01-18
申请号：US15545901
申请日：2015-01-30
发明人： Sanketh Nalli , Haris Volos , Kimberly Keeton
IPC分类号： G06F12/02
CPC分类号： G06F12/0238 , G06F12/0804 , G06F12/0868 , G06F2212/1028 , G06F2212/1032 , G06F2212/7203 , Y02D10/13
摘要： Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.
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公开(公告)号：US10854331B2
公开(公告)日：2020-12-01
申请号：US15522246
申请日：2014-10-26
IPC分类号： G06F16/2453 , G16H40/63 , G06F16/25 , G06F17/14 , G06F17/18
摘要： A transformation on raw data is applied to produce transformed data, where the transformation includes at least one selected from among a summary of the raw data or a transform of the raw data between different domains. In response to a query to access data, the query is processed using the transformed data.
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公开(公告)号：US20190121750A1
公开(公告)日：2019-04-25
申请号：US15789431
申请日：2017-10-20
IPC分类号： G06F12/14 , G06F12/128
摘要： Determining cache value currency using persistent markers is disclosed herein. In one example, a cache entry is retrieved from a local cache memory device. The cache entry includes a key, a value to be used by the computing device, and a marker flag to determine whether the cache entry is current. The local cache memory device also includes a marker location that indicates a location of a marker in a shared persistent fabric-attached memory (FAM). Using a marker location, the marker is retrieved from the shared persistent FAM. From the marker and the marker flag, it is determined whether the cache entry is current. The shared FAM pool is connected to the local cache memory devices of multiple computing devices.
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公开(公告)号：US20190012095A1
公开(公告)日：2019-01-10
申请号：US16065778
申请日：2016-01-22
摘要： Techniques for injecting a delay to simulate latency are provided. In one aspect, it may be determined that a current epoch should end. A delay may be injected. The delay may simulate the latency of non-volatile memory access during the current epoch. The current epoch may then end. A new epoch may then begin.
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公开(公告)号：US20180357001A1
公开(公告)日：2018-12-13
申请号：US16061221
申请日：2015-12-16
IPC分类号： G06F3/06
CPC分类号： G06F3/0631 , G06F3/0604 , G06F3/0664 , G06F3/0679 , G06F12/02
摘要： Techniques for allocating memory based on memory type request are provided. In one aspect, an application thread may be bound to a first processor. The first processor may be associated with a first memory. A portion of memory may be allocated from the first memory in response to the application thread requesting memory of a first type. A portion of memory from a second memory associated with a second processor may be allocated in response to the application thread requesting memory of a second type.
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公开(公告)号：US20180300083A1
公开(公告)日：2018-10-18
申请号：US15485399
申请日：2017-04-12
发明人： Haris Volos , Hideaki Kimura , James Park , Daniel Fryer
IPC分类号： G06F3/06
摘要： An example system for write-ahead logging through a plurality of logging buffers using a non-volatile memory (NVM) is disclosed. The example disclosed herein comprises a processing unit coupled to one or more controllers from one or more client applications. The example also comprises a plurality of logging buffers to receive a plurality of first log data threads based on a predetermined timestamp range, wherein each log buffer stores a single first timestamp log data thread from a plurality of timestamp log data threads. The example further comprises a flusher to flush the plurality of first timestamp log data threads from the plurality of logging buffers to a first timestamp log data. The flusher stores the first timestamp log data to an NVM to build flushed timestamp log data. The example further comprises a syncer to sync the flushed timestamp log data from the NVM to an HD device in time stamp sequential order.
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