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    Compact, high power supply rejection ratio, low power semiconductor digitally controlled oscillator architecture
    1.
    发明授权
    Compact, high power supply rejection ratio, low power semiconductor digitally controlled oscillator architecture 有权
    紧凑，高电源抑制比，低功耗半导体数字控制振荡器架构

    公开(公告)号：US06784755B2

    公开(公告)日：2004-08-31

    申请号：US10292276

    申请日：2002-11-12

    申请人： Heng-Chih Lin ,  Baher S. Haroun

    发明人： Heng-Chih Lin ,  Baher S. Haroun

    IPC分类号： H03B100

    CPC分类号： H03L7/0995 ,  H03K3/0322

    摘要： A high PSRR, low power semiconductor digitally controlled oscillator (DCO) architecture employs only one simple current steering D/A converter directly on top of a multi-stage current controlled oscillator. The architecture provides a good building block for many circuit applications, e.g., all digital phase lock loops, direct modulation transmitters for wireless devices, and the like.

    摘要翻译： 高PSRR低功耗半导体数字控制振荡器（DCO）架构直接在多级电流控制振荡器的顶部仅使用一个简单的电流导引D / A转换器。 该架构为许多电路应用提供了良好的构建块，例如所有数字锁相环，用于无线设备的直接调制发射机等。

    Wide band, wide operation range, general purpose digital phase locked loop architecture
    2.
    发明授权
    Wide band, wide operation range, general purpose digital phase locked loop architecture 有权
    宽带宽，操作范围广泛，通用数字锁相环架构

    公开(公告)号：US06798296B2

    公开(公告)日：2004-09-28

    申请号：US10292225

    申请日：2002-11-12

    申请人： Heng-Chih Lin ,  Baher S. Haroun ,  Tiang Tun Foo

    发明人： Heng-Chih Lin ,  Baher S. Haroun ,  Tiang Tun Foo

    IPC分类号： H03L700

    CPC分类号： H03K3/0322 ,  H03K5/1252 ,  H03L7/089 ,  H03L7/093 ,  H03L7/18 ,  H03L2207/50

    摘要： A wide band, wide operating range, general purpose digital phase locked loop (PLL) runs in the digital domain except for the associated Time Digitizer (T2D) and Digitally-Controlled-Oscillator (DCO). By calibrating the T2D and DCO on the fly, a constant PLL loop BW is achieved by using the calibrated Phase Frequency Detection (PFD) and DCO information to normalize the control loop correction regardless of the input clock frequency, power supply voltage, processing and temperature variations. PLL loop BW is completely decoupled from the operating conditions and semiconductor device variation. This means that the PLL loop BW can be chosen very aggressively to reject the noise, thus achieving a low jitter, high performance PLL. Furthermore, since this PLL can reliably operate over a wide operating range, it is a one-design-fits-all general purpose PLL.

    摘要翻译： 宽带，宽工作范围，通用数字锁相环（PLL）在数字域内运行，除了相关的时间数字转换器（T2D）和数字控制振荡器（DCO）外。 通过快速校准T2D和DCO，无论输入时钟频率，电源电压，处理和温度如何，通过使用校准的相位频率检测（PFD）和DCO信息来对控制回路校正进行归一化来实现恒定的PLL环路BW 变化。 PLL环路BW与操作条件和半导体器件变化完全解耦。 这意味着可以非常积极地选择PLL环路BW来抑制噪声，从而实现低抖动，高性能的PLL。 此外，由于该PLL可以在宽的工作范围内可靠地工作，所以它是一个单一设计的通用PLL。

    Glitch free clock multiplexing circuit with asynchronous switch control and minimum switch over time
    3.
    发明授权
    Glitch free clock multiplexing circuit with asynchronous switch control and minimum switch over time 有权
    无毛刺时钟多路复用电路，具有异步开关控制和最小开关时间

    公开(公告)号：US06784699B2

    公开(公告)日：2004-08-31

    申请号：US10292243

    申请日：2002-11-12

    申请人： Baher S. Haroun ,  Heng-Chih Lin ,  Tim Foo

    发明人： Baher S. Haroun ,  Heng-Chih Lin ,  Tim Foo

    IPC分类号： H03K1700

    CPC分类号： G06F1/08 ,  H03K3/0322 ,  H03K5/1252 ,  H03L7/093 ,  H03L7/18 ,  H03L2207/50

    摘要： A symmetric glitch free clock multiplexing circuit allows the input clock to a digital or analog processing unit to be switched from one frequency to the other at any moment during the operation, assuming the respective clocks themselves are stable. There exist no restrictions on the clocks or the switch control signal to be synchronous in any fashion. This circuit guarantees a glitch free output and also prevents short cycling of the output clock. Since all the related clocks and switch control signal are asynchronous, this circuit further eliminates meta-stability problems. Its symmetrical architecture allows the circuit to function with the output clock being switched from slow clock to fast clock and vise versa. More importantly, the complete switch over only takes two cycles of the targeted clock in the best case once the active clock is turned off, when switching from slow to fast clock; and four target clock cycles in the worst case once the active clock is turned off, when switching from fast to slow clock.

    摘要翻译： 假设相应的时钟本身是稳定的，对称无毛刺时钟多路复用电路允许在操作期间的任何时刻将数字或模拟处理单元的输入时钟从一个频率切换到另一个频率。 时钟或开关控制信号不以任何方式同步的限制。 该电路保证无毛刺输出，并且还可以防止输出时钟的短暂循环。 由于所有相关时钟和开关控制信号都是异步的，因此该电路进一步消除了元稳定性问题。 其对称架构允许电路工作，输出时钟从慢时钟切换到快时钟，反之亦然。 更重要的是，一旦活动时钟关闭，当从慢速切换到快速时钟时，完全切换只需要两个周期的目标时钟; 在最坏情况下，一旦活动时钟关闭，当从快速切换到慢时钟时，则有四个目标时钟周期。

    Precise differential voltage interpolation analog-to-digital converter having double interpolation using nonlinear resistors
    4.
    发明授权
    Precise differential voltage interpolation analog-to-digital converter having double interpolation using nonlinear resistors 有权
    精密差分电压内插模数转换器，使用非线性电阻进行双插补

    公开(公告)号：US06614379B2

    公开(公告)日：2003-09-02

    申请号：US10027710

    申请日：2001-12-20

    申请人： Heng-Chih Lin ,  Baher S. Haroun

    发明人： Heng-Chih Lin ,  Baher S. Haroun

    IPC分类号： H03M112

    CPC分类号： H03M1/205 ,  H03M1/0682 ,  H03M1/365

    摘要： A flash analog-to-digital converter having precise differential voltage interpolation without the use of silicide-blocked resistors. A reference conversion voltage output portion converts an analog input voltage on the basis of a plurality of reference voltages into a plurality of reference conversion voltages. An intermediate voltage generating portion includes a predetermined number of non-linear resistance units respectively provided between one voltage and the other voltage in pairs of a predetermined number of the plurality of reference conversion voltages to generate a plurality of intermediate voltages by resistance division using the predetermined number of non-linear resistance units. In addition, the intermediate voltage generating portion generates a plurality of conversion voltages. A digital data output portion outputs the digital output voltage on the basis of the plurality of conversion voltages using double interpolation. Each of the predetermined number of non-linear resistance units includes a first input terminal connected to the one voltage, a second input terminal connected to the other voltage, and a plurality of non-linear resistor elements having the same resistance value connected in series between the first and second input terminals. The plurality of intermediate voltages includes at least part of voltages obtained from one end of each of the plurality of non-linear resistor elements.

    摘要翻译： 具有精确差分电压内插的闪存模数转换器，不使用硅化物阻挡电阻。 参考转换电压输出部分将基于多个参考电压的模拟输入电压转换为多个参考转换电压。 中间电压产生部分包括预定数量的非线性电阻单元，其分别设置在预定数量的多个基准转换电压中的成对中的一个电压和另一个电压之间，以通过使用预定的电压分压产生多个中间电压 非线性电阻单位数。 此外，中间电压产生部分产生多个转换电压。 数字数据输出部分使用双插值来输出基于多个转换电压的数字输出电压。 预定数量的非线性电阻单元中的每一个包括连接到一个电压的第一输入端子，连接到另一个电压的第二输入端子以及具有串联连接的相同电阻值的多个非线性电阻器元件 第一和第二输入端子。 多个中间电压包括从多个非线性电阻元件中的每一个的一端获得的电压的至少一部分。

    ANALOG BASEBAND CIRCUIT FOR A TERAHERTZ PHASED ARRAY SYSTEM
    6.
    发明申请
    ANALOG BASEBAND CIRCUIT FOR A TERAHERTZ PHASED ARRAY SYSTEM 有权
    用于TERAHERTZ相位阵列的模拟基带电路

    公开(公告)号：US20120261579A1

    公开(公告)日：2012-10-18

    申请号：US13085264

    申请日：2011-04-12

    申请人： Srinath M. Ramaswamy ,  Vijay B. Rentala ,  Brian P. Ginsburg ,  Baher S. Haroun ,  Eunyoung Seok

    发明人： Srinath M. Ramaswamy ,  Vijay B. Rentala ,  Brian P. Ginsburg ,  Baher S. Haroun ,  Eunyoung Seok

    IPC分类号： G01J5/26 ,  G01J5/02

    CPC分类号： H01Q3/26 ,  G01S7/288 ,  G01S13/426

    摘要： A method for determining the position of a target is provided. Several emitted pulses of terahertz radiations are emitted from a phased array (which has several transceivers) in consecutive cycles (typically). These emitted pulses are generally configured to be reflected by a target so as to be received by the phased array within a scan range (which includes a digitization window with several sampling periods). Output signals from each of the transceivers are then combined to generate a combined signal for each cycle. The combined signal in each sampling period within the digitization window for emitted pulses is averaged to generate an averaged signal for each sampling period within the digitization window. These averaged signals are then digitized.

    摘要翻译： 提供了一种用于确定目标位置的方法。 几个发射的太赫兹辐射脉冲从相控阵列（其具有几个收发器）以连续的周期（通常）发射。 这些发射脉冲通常被配置为被目标物反射，以便在扫描范围内包括相控阵列（其包括具有多个采样周期的数字化窗口）。 然后将来自每个收发器的输出信号组合以产生每个周期的组合信号。 在发射脉冲的数字化窗口内的每个采样周期中的组合信号被平均以产生数字化窗口内的每个采样周期的平均信号。 然后将这些平均信号数字化。

    DOWNCONVERSION MIXER
    8.
    发明申请
    DOWNCONVERSION MIXER 有权
    DOWNCONVERSION混合器

    公开(公告)号：US20120049972A1

    公开(公告)日：2012-03-01

    申请号：US12871626

    申请日：2010-08-30

    申请人： Brian P. Ginsburg ,  Vijay B. Rentala ,  Srinath M. Ramaswamy ,  Baher S. Haroun ,  Eunyoung Seok

    发明人： Brian P. Ginsburg ,  Vijay B. Rentala ,  Srinath M. Ramaswamy ,  Baher S. Haroun ,  Eunyoung Seok

    IPC分类号： H01P1/10 ,  H01P5/18

    CPC分类号： H01P5/184 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/165 ,  H03D2200/0023

    摘要： At very high frequencies, generally above 100 GHz, the performance of traditional radio frequency (RF) circuitry begins to significantly limit performance. An example is the hybrid coupler, which can have a relatively narrow 90° bandwidth in these frequency ranges. Here, however, a branch-line hybrid coupler (which has been integrated into a quadrature downconversion mixer) has been modified. Namely, an adjustable impedance network has been coupled to isolation port (which has traditionally been terminated) to substantially increase the tuning range and expand the bandwidth of the quadrature mixer within these very high frequency ranges.

    摘要翻译： 在非常高的频率（通常在100GHz以上），传统射频（RF）电路的性能开始显着地限制性能。 一个例子是混合耦合器，其在这些频率范围内可以具有相对窄的90°带宽。 然而，这里已经修改了分支线路混合耦合器（其已被集成到正交下变频混频器中）。 也就是说，可调阻抗网络已经耦合到隔离端口（传统上已被终止），以显着增加调谐范围并且在这些非常高的频率范围内扩大正交混频器的带宽。

    TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS
    10.
    发明申请
    TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS 有权
    用于IEEE 1149.1测试访问端口的多个光纤扫描接入的TAP和链接模块

    公开(公告)号：US20100162061A1

    公开(公告)日：2010-06-24

    申请号：US12539373

    申请日：2009-08-11

    申请人： Baher S. Haroun ,  Lee D. Whetsel

    发明人： Baher S. Haroun ,  Lee D. Whetsel

    IPC分类号： G01R31/3177 ,  G06F11/25

    CPC分类号： G01R31/3177 ,  G01R31/2851 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318558 ,  G11C29/46

    摘要： An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

    摘要翻译： 描述了用于在集成电路上测试多个电路的架构。 该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。