公开(公告)号：US08030205B2

公开(公告)日：2011-10-04

申请号：US12618523

申请日：2009-11-13

申请人： Hae-Jung Lee ,  Sang-Hoon Cho ,  Suk-Ki Kim

发明人： Hae-Jung Lee ,  Sang-Hoon Cho ,  Suk-Ki Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/76843 ,  H01L21/76849

摘要： A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成层间绝缘层; 在层间绝缘层中形成开口; 在开口和层间绝缘层上形成金属阻挡层; 在所述金属阻挡层上形成第一导电层并填充在所述开口中; 蚀刻所述第一导电层以在所述开口中形成互连层并且暴露所述金属阻挡层的部分，所述互连层位于所述开口内部以及在距所述开口顶部的深度处; 蚀刻金属阻挡层的暴露部分以在开口的顶侧部分处获得金属阻挡层的倾斜轮廓; 在所述层间绝缘层上形成第二导电层，所述互连层和所述金属阻挡层具有所述倾斜轮廓; 并且图案化第二导电层以形成金属线。

公开(公告)号：US07648909B2

公开(公告)日：2010-01-19

申请号：US11321533

申请日：2005-12-30

申请人： Hae-Jung Lee ,  Sang-Hoon Cho ,  Suk-Ki Kim

发明人： Hae-Jung Lee ,  Sang-Hoon Cho ,  Suk-Ki Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/76843 ,  H01L21/76849

摘要： A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成层间绝缘层; 在层间绝缘层中形成开口; 在开口和层间绝缘层上形成金属阻挡层; 在所述金属阻挡层上形成第一导电层并填充在所述开口中; 蚀刻所述第一导电层以在所述开口中形成互连层并且暴露所述金属阻挡层的部分，所述互连层位于所述开口内部以及在距所述开口顶部的深度处; 蚀刻金属阻挡层的暴露部分以在开口的顶侧部分处获得金属阻挡层的倾斜轮廓; 在所述层间绝缘层上形成第二导电层，所述互连层和所述金属阻挡层具有所述倾斜轮廓; 并且图案化第二导电层以形成金属线。

公开(公告)号：US20060246708A1

公开(公告)日：2006-11-02

申请号：US11321533

申请日：2005-12-30

申请人： Hae-Jung Lee ,  Sang-Hoon Cho ,  Suk-Ki Kim

发明人： Hae-Jung Lee ,  Sang-Hoon Cho ,  Suk-Ki Kim

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/76843 ,  H01L21/76849

摘要： A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成层间绝缘层; 在层间绝缘层中形成开口; 在开口和层间绝缘层上形成金属阻挡层; 在所述金属阻挡层上形成第一导电层并填充在所述开口中; 蚀刻所述第一导电层以在所述开口中形成互连层并且暴露所述金属阻挡层的部分，所述互连层位于所述开口内部以及在距所述开口顶部的深度处; 蚀刻金属阻挡层的暴露部分以在开口的顶侧部分处获得金属阻挡层的倾斜轮廓; 在所述层间绝缘层上形成第二导电层，所述互连层和所述金属阻挡层具有所述倾斜轮廓; 并且图案化第二导电层以形成金属线。

公开(公告)号：US20070004194A1

公开(公告)日：2007-01-04

申请号：US11321593

申请日：2005-12-30

申请人： Yong-Tae Cho ,  Hae-Jung Lee ,  Sang-Hoon Cho

发明人： Yong-Tae Cho ,  Hae-Jung Lee ,  Sang-Hoon Cho

IPC分类号： H01L21/4763

CPC分类号： H01L27/10852 ,  H01L21/76802 ,  H01L21/76844

摘要： A method for fabricating a semiconductor device with a deep opening is provided. The method includes: forming an insulation layer on a substrate; selectively etching the insulation layer to form first openings; enlarging areas of the first openings; forming anti-bowing spacers on sidewalls of the enlarged first openings; and etching portions of the insulation layer remaining beneath the enlarged first openings to form second openings.

摘要翻译： 提供一种制造具有深开口的半导体器件的方法。 该方法包括：在基板上形成绝缘层; 选择性地蚀刻绝缘层以形成第一开口; 扩大开放区域; 在扩大的第一开口的侧壁上形成抗弓形间隔物; 以及蚀刻保留在扩大的第一开口下方的部分以形成第二开口。

公开(公告)号：US08003485B2

公开(公告)日：2011-08-23

申请号：US12318466

申请日：2008-12-30

申请人： Yong-Tae Cho ,  Hae-Jung Lee ,  Eun-Mi Kim ,  Kyeong-Hyo Lee

发明人： Yong-Tae Cho ,  Hae-Jung Lee ,  Eun-Mi Kim ,  Kyeong-Hyo Lee

IPC分类号： H01L29/78 ,  H01L21/762

CPC分类号： H01L29/66795 ,  H01L29/7851

摘要： In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.

摘要翻译： 在制造半导体器件及其相关方法中，在衬底上形成硬掩模层，硬掩模层和衬底的部分被蚀刻以形成在侧壁具有突出部分的沟槽，并且埋在沟槽中的绝缘层 被形成以形成在侧壁具有突出部分的器件隔离区域，其中器件隔离区域减小有效区域宽度的一部分。

公开(公告)号：US20110159687A1

公开(公告)日：2011-06-30

申请号：US12833081

申请日：2010-07-09

申请人： Hae-Jung Lee ,  Kang-Pok Lee ,  Kyeong-Hyo Lee

发明人： Hae-Jung Lee ,  Kang-Pok Lee ,  Kyeong-Hyo Lee

IPC分类号： H01L21/3213

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/32135

摘要： A method for fabricating a semiconductor device includes forming a plurality of plugs over a die region and an edge bead removal (EBR) region of a wafer, forming metal lines coupled to the plugs, removing the metal lines in the EBR region, forming an inter-layer dielectric layer over the wafer, and forming a plurality of contact holes that expose the metal lines by selectively etching the inter-layer dielectric layer through a dry etch process using a plasma etch device.

摘要翻译： 一种制造半导体器件的方法包括在晶片的芯片区域和边缘珠去除（EBR）区域上形成多个插塞，形成耦合到插塞的金属线，去除EBR区域中的金属线， 并且通过使用等离子体蚀刻装置的干蚀刻工艺选择性地蚀刻层间电介质层而形成多个接触孔，以暴露金属线。

公开(公告)号：US20070148979A1

公开(公告)日：2007-06-28

申请号：US11413162

申请日：2006-04-28

申请人： Hae-Jung Lee ,  Yong-Tae Cho

发明人： Hae-Jung Lee ,  Yong-Tae Cho

IPC分类号： C23F1/00 ,  H01L21/461 ,  B44C1/22 ,  H01L21/302

CPC分类号： H01L21/3065 ,  H01L21/3081 ,  H01L29/4236 ,  H01L29/66621

摘要： A method for forming a semiconductor device having a recess pattern with a rounded top corner is provided. The method includes forming an etch mask pattern including a patterned sacrificial layer and a patterned hard mask layer over a substrate; etching predetermined portions of exposed sidewalls of the patterned sacrificial layer to form an undercut; etching the substrate to a predetermined depth using the etch mask pattern as an etch mask to form a recess having top corners; and performing an isotropic etching process to round the top corners of the recess beneath the undercut.

摘要翻译： 提供了一种用于形成具有带有圆角顶角的凹陷图案的半导体器件的方法。 该方法包括在衬底上形成包括图案化牺牲层和图案化硬掩模层的蚀刻掩模图案; 蚀刻图案化牺牲层的暴露的侧壁的预定部分以形成底切; 使用蚀刻掩模图案作为蚀刻掩模将衬底蚀刻到预定深度，以形成具有顶角的凹部; 并执行各向同性蚀刻工艺以使底切下方的凹部的顶角圆角。

公开(公告)号：US08426257B2

公开(公告)日：2013-04-23

申请号：US12004179

申请日：2007-12-20

申请人： Hyun-Sik Park ,  Hae-Jung Lee ,  Jae-Kyun Lee

发明人： Hyun-Sik Park ,  Hae-Jung Lee ,  Jae-Kyun Lee

IPC分类号： H01L27/10

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device includes forming a fuse over a substrate, the fuse having a barrier layer, a metal layer, and an anti-reflective layer stacked, selectively removing the anti-reflective layer, forming an insulation layer over a whole surface of the resultant structure including the fuse, and performing repair-etching such that part of the insulation layer remains above the fuse.

摘要翻译： 一种用于制造半导体器件的方法，包括在衬底上形成熔丝，所述熔丝具有阻挡层，金属层和抗反射层，层叠，选择性地去除抗反射层，在整个表面上形成绝缘层 包括保险丝的所得结构，并执行修补蚀刻，使得绝缘层的一部分保留在保险丝上方。

公开(公告)号：US20070123040A1

公开(公告)日：2007-05-31

申请号：US11418720

申请日：2006-05-05

申请人： Chang-Youn Hwang ,  Hyung-Hwan Kim ,  Ik-Soo Choi ,  Hae-Jung Lee

发明人： Chang-Youn Hwang ,  Hyung-Hwan Kim ,  Ik-Soo Choi ,  Hae-Jung Lee

IPC分类号： H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/76804 ,  H01L21/76831 ,  H01L27/10855

摘要： A method for forming a storage node contact plug in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer over a substrate having a conductive plug; etching a portion of the inter-layer insulation layer using at least line type storage node contact masks as an etch mask to form a first contact hole with sloping sidewalls; etching another portion of the inter-layer insulation layer underneath the first contact hole to form a second contact hole exposing the conductive plug, the second contact hole having substantially vertical sidewalls; and filling the first and second storage node contact holes to form a storage node contact plug.

摘要翻译： 提供一种在半导体器件中形成存储节点接触插头的方法。 该方法包括：在具有导电插塞的基板上形成层间绝缘层; 使用至少线型存储节点接触掩模作为蚀刻掩模蚀刻层间绝缘层的一部分，以形成具有倾斜侧壁的第一接触孔; 蚀刻在第一接触孔下面的层间绝缘层的另一部分，以形成露出导电插塞的第二接触孔，第二接触孔具有基本垂直的侧壁; 以及填充所述第一和第二存储节点接触孔以形成存储节点接触插头。

公开(公告)号：US20070004181A1

公开(公告)日：2007-01-04

申请号：US11363913

申请日：2006-02-27

申请人： Yong-Tae Cho ,  Hae-Jung Lee

发明人： Yong-Tae Cho ,  Hae-Jung Lee

IPC分类号： H01L21/326

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a region in which a fuse is formed is provided. The method includes forming a first insulation layer over a substrate, forming a plurality of fuses over the first insulation layer, forming a second insulation layer to cover the fuses, forming an etch stop layer over the second insulation layer, forming a metal layer over a predetermined portion of the etch stop layer, forming a third insulation layer to cover the metal layer, performing a pad/repair process on the third insulation layer until the metal layer and the etch stop layer are exposed, and selectively removing the exposed portion of the etch stop layer and the second insulation layer.

摘要翻译： 提供一种用于制造其中形成熔丝的区域的方法。 该方法包括在衬底上形成第一绝缘层，在第一绝缘层上形成多个熔丝，形成第二绝缘层以覆盖熔丝，在第二绝缘层上形成蚀刻停止层，在第一绝缘层上形成金属层 形成蚀刻停止层的预定部分，形成覆盖金属层的第三绝缘层，在第三绝缘层上进行焊接/修复处理，直到暴露金属层和蚀刻停止层，并选择性地去除暴露部分 蚀刻停止层和第二绝缘层。