公开(公告)号：US20070004194A1

公开(公告)日：2007-01-04

申请号：US11321593

申请日：2005-12-30

申请人： Yong-Tae Cho ,  Hae-Jung Lee ,  Sang-Hoon Cho

发明人： Yong-Tae Cho ,  Hae-Jung Lee ,  Sang-Hoon Cho

IPC分类号： H01L21/4763

CPC分类号： H01L27/10852 ,  H01L21/76802 ,  H01L21/76844

摘要： A method for fabricating a semiconductor device with a deep opening is provided. The method includes: forming an insulation layer on a substrate; selectively etching the insulation layer to form first openings; enlarging areas of the first openings; forming anti-bowing spacers on sidewalls of the enlarged first openings; and etching portions of the insulation layer remaining beneath the enlarged first openings to form second openings.

摘要翻译： 提供一种制造具有深开口的半导体器件的方法。 该方法包括：在基板上形成绝缘层; 选择性地蚀刻绝缘层以形成第一开口; 扩大开放区域; 在扩大的第一开口的侧壁上形成抗弓形间隔物; 以及蚀刻保留在扩大的第一开口下方的部分以形成第二开口。

公开(公告)号：US07858476B2

公开(公告)日：2010-12-28

申请号：US11928056

申请日：2007-10-30

申请人： Yong-Tae Cho ,  Suk-Ki Kim ,  Sang-Hoon Cho

发明人： Yong-Tae Cho ,  Suk-Ki Kim ,  Sang-Hoon Cho

IPC分类号： H01L21/336

CPC分类号： H01L29/66621 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/3086

摘要： A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming a first recess in the substrate and a passivation layer on sidewalls of the first recess using the hard mask pattern as an etch barrier, and forming a second recess by etching a bottom portion of the first recess using the passivation layer as an etch barrier, wherein a width of the second recess is greater than that of the first recess.

摘要翻译： 一种用于制造半导体器件的方法包括：在衬底上形成硬掩模图案，在衬底中形成第一凹槽，并使用硬掩模图案作为蚀刻阻挡层，在第一凹槽的侧壁上形成钝化层，并形成第二凹槽 使用钝化层蚀刻第一凹部的底部作为蚀刻阻挡层，其中第二凹部的宽度大于第一凹部的宽度。

公开(公告)号：US08003485B2

公开(公告)日：2011-08-23

申请号：US12318466

申请日：2008-12-30

申请人： Yong-Tae Cho ,  Hae-Jung Lee ,  Eun-Mi Kim ,  Kyeong-Hyo Lee

发明人： Yong-Tae Cho ,  Hae-Jung Lee ,  Eun-Mi Kim ,  Kyeong-Hyo Lee

IPC分类号： H01L29/78 ,  H01L21/762

CPC分类号： H01L29/66795 ,  H01L29/7851

摘要： In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.

摘要翻译： 在制造半导体器件及其相关方法中，在衬底上形成硬掩模层，硬掩模层和衬底的部分被蚀刻以形成在侧壁具有突出部分的沟槽，并且埋在沟槽中的绝缘层 被形成以形成在侧壁具有突出部分的器件隔离区域，其中器件隔离区域减小有效区域宽度的一部分。

公开(公告)号：US20070148979A1

公开(公告)日：2007-06-28

申请号：US11413162

申请日：2006-04-28

申请人： Hae-Jung Lee ,  Yong-Tae Cho

发明人： Hae-Jung Lee ,  Yong-Tae Cho

IPC分类号： C23F1/00 ,  H01L21/461 ,  B44C1/22 ,  H01L21/302

CPC分类号： H01L21/3065 ,  H01L21/3081 ,  H01L29/4236 ,  H01L29/66621

摘要： A method for forming a semiconductor device having a recess pattern with a rounded top corner is provided. The method includes forming an etch mask pattern including a patterned sacrificial layer and a patterned hard mask layer over a substrate; etching predetermined portions of exposed sidewalls of the patterned sacrificial layer to form an undercut; etching the substrate to a predetermined depth using the etch mask pattern as an etch mask to form a recess having top corners; and performing an isotropic etching process to round the top corners of the recess beneath the undercut.

摘要翻译： 提供了一种用于形成具有带有圆角顶角的凹陷图案的半导体器件的方法。 该方法包括在衬底上形成包括图案化牺牲层和图案化硬掩模层的蚀刻掩模图案; 蚀刻图案化牺牲层的暴露的侧壁的预定部分以形成底切; 使用蚀刻掩模图案作为蚀刻掩模将衬底蚀刻到预定深度，以形成具有顶角的凹部; 并执行各向同性蚀刻工艺以使底切下方的凹部的顶角圆角。

公开(公告)号：US08487399B2

公开(公告)日：2013-07-16

申请号：US13184235

申请日：2011-07-15

申请人： Yong-Tae Cho ,  Hae-Jung Lee ,  Eun-Mi Kim ,  Kyeong-Hyo Lee

发明人： Yong-Tae Cho ,  Hae-Jung Lee ,  Eun-Mi Kim ,  Kyeong-Hyo Lee

IPC分类号： H01L27/10

CPC分类号： H01L29/66795 ,  H01L29/7851

摘要： In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.

摘要翻译： 在制造半导体器件及其相关方法中，在衬底上形成硬掩模层，硬掩模层和衬底的部分被蚀刻以形成在侧壁具有突出部分的沟槽，并且埋在沟槽中的绝缘层 被形成以形成在侧壁具有突出部分的器件隔离区域，其中器件隔离区域减小有效区域宽度的一部分。

公开(公告)号：US20070004181A1

公开(公告)日：2007-01-04

申请号：US11363913

申请日：2006-02-27

申请人： Yong-Tae Cho ,  Hae-Jung Lee

发明人： Yong-Tae Cho ,  Hae-Jung Lee

IPC分类号： H01L21/326

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a region in which a fuse is formed is provided. The method includes forming a first insulation layer over a substrate, forming a plurality of fuses over the first insulation layer, forming a second insulation layer to cover the fuses, forming an etch stop layer over the second insulation layer, forming a metal layer over a predetermined portion of the etch stop layer, forming a third insulation layer to cover the metal layer, performing a pad/repair process on the third insulation layer until the metal layer and the etch stop layer are exposed, and selectively removing the exposed portion of the etch stop layer and the second insulation layer.

摘要翻译： 提供一种用于制造其中形成熔丝的区域的方法。 该方法包括在衬底上形成第一绝缘层，在第一绝缘层上形成多个熔丝，形成第二绝缘层以覆盖熔丝，在第二绝缘层上形成蚀刻停止层，在第一绝缘层上形成金属层 形成蚀刻停止层的预定部分，形成覆盖金属层的第三绝缘层，在第三绝缘层上进行焊接/修复处理，直到暴露金属层和蚀刻停止层，并选择性地去除暴露部分 蚀刻停止层和第二绝缘层。

公开(公告)号：US08604561B2

公开(公告)日：2013-12-10

申请号：US13184272

申请日：2011-07-15

申请人： Yong-Tae Cho ,  Hae-Jung Lee ,  Eun-Mi Kim ,  Kyeong-Hyo Lee

发明人： Yong-Tae Cho ,  Hae-Jung Lee ,  Eun-Mi Kim ,  Kyeong-Hyo Lee

IPC分类号： H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/7851

摘要： In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.

公开(公告)号：US20100025806A1

公开(公告)日：2010-02-04

申请号：US12318466

申请日：2008-12-30

申请人： Yong-Tae Cho ,  Hae-Jung Lee ,  Eun-Mi Kim ,  Kyeong-Hyo Lee

发明人： Yong-Tae Cho ,  Hae-Jung Lee ,  Eun-Mi Kim ,  Kyeong-Hyo Lee

IPC分类号： H01L29/78 ,  H01L21/762

CPC分类号： H01L29/66795 ,  H01L29/7851

摘要： In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.

摘要翻译： 在制造半导体器件及其相关方法中，在衬底上形成硬掩模层，硬掩模层和衬底的部分被蚀刻以形成在侧壁具有突出部分的沟槽，并且埋在沟槽中的绝缘层 被形成以形成在侧壁具有突出部分的器件隔离区域，其中器件隔离区域减小有效区域宽度的一部分。

公开(公告)号：US07553767B2

公开(公告)日：2009-06-30

申请号：US11455847

申请日：2006-06-20

申请人： Yong-Tae Cho ,  Eun-Mi Kim

发明人： Yong-Tae Cho ,  Eun-Mi Kim

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76232

摘要： A method for fabricating a semiconductor includes: etching a substrate to a predetermined depth to form an upper trench with taper edges; etching the substrate beneath the upper trench to form a lower trench with approximately vertical edges; forming a device isolation layer disposed within the upper and lower trenches; and etching an active region of the substrate defined by the upper and lower trenches to a predetermined depth to form a recess pattern for a gate.

摘要翻译： 一种制造半导体的方法包括：将衬底蚀刻到预定深度以形成具有锥形边缘的上沟槽; 蚀刻在上沟槽下方的衬底以形成具有大致垂直边缘的下沟槽; 形成设置在所述上​​沟槽和下沟槽内的器件隔离层; 并且将由所述上沟槽和下沟槽限定的衬底的有源区域蚀刻到预定深度以形成用于栅极的凹陷图案。

公开(公告)号：US20070148934A1

公开(公告)日：2007-06-28

申请号：US11411891

申请日：2006-04-27

申请人： Yong-Tae Cho ,  Suk-Ki Kim

发明人： Yong-Tae Cho ,  Suk-Ki Kim

IPC分类号： H01L21/3205

CPC分类号： H01L21/3065 ,  H01L29/66621

摘要： A method for fabricating a semiconductor device with a bulb shaped recess gate pattern includes selectively etching a first portion of a substrate to form a first recess; forming a spacer on sidewalls of the first recess; performing an isotropic etching process on a second portion of the substrate beneath the first recess to form a second recess, the second recess being wider and more rounded than the first recess; removing the spacer; and forming a gate pattern having a first portion buried into the first and second recesses and a second portion projecting over the substrate.

摘要翻译： 一种用于制造具有灯泡形凹槽栅极图案的半导体器件的方法，包括选择性地蚀刻衬底的第一部分以形成第一凹槽; 在所述第一凹槽的侧壁上形成间隔物; 在所述第一凹部下面的所述基底的第二部分上进行各向同性蚀刻工艺以形成第二凹部，所述第二凹部比所述第一凹部更宽且更圆; 去除间隔物; 以及形成具有掩埋在所述第一和第二凹部中的第一部分的栅极图案和在所述基板上突出的第二部分。