DATA PROCESSING METHOD AND SYSTEM BASED ON QUASI-CYCLIC LDPC

    公开(公告)号:US20170302294A1

    公开(公告)日:2017-10-19

    申请号:US15638014

    申请日:2017-06-29

    Abstract: A data processing method based on a quasi-cyclic LDPC includes: when a size of service data is less than a magnitude of information bit of the quasi-cyclic LDPC, calculating a difference value between the magnitude of the information bit of the quasi-cyclic LDPC and the size of the service data, and filling the service data with the same amount of known data as the difference value (S103); coding the filled service data to obtain redundancy check data corresponding to the service data (S104); and sending the service data and the redundancy check data to a corresponding physical location in the storage unit (S105). It ensures that when a code length of the quasi-cyclic LDPC is constant, the code length ideally adapts to internal space of the storage unit, and the quasi-cyclic LDPC has a relatively high error correction capability, thereby improving reliability and service life of the storage unit.

    HIGH ORDER MODULATION METHOD, DEMAPPING METHOD, AND CORRESPONDING DEVICE
    3.
    发明申请
    HIGH ORDER MODULATION METHOD, DEMAPPING METHOD, AND CORRESPONDING DEVICE 有权
    高阶调制方法,调制方法和相应的器件

    公开(公告)号:US20150103956A1

    公开(公告)日:2015-04-16

    申请号:US14577734

    申请日:2014-12-19

    Abstract: A high order modulation method, a demapping method, and a corresponding device are provided. With the high order modulation method, important bits is distinguished, and the important bits are divided into important bits for distinguishing large regions and important bits for distinguishing small regions according to the difficulty of judgment areas. Therefore, the judgment accuracy rate of a demodulator is further improved.

    Abstract translation: 提供了高阶调制方法,解映射方法和相应的装置。 利用高阶调制方式,重要的比特被区分开来,根据判断区域的难度,将重要的比特划分成用于区分大区域和重要比特用于区分小区域的重要比特。 因此,解调器的判断准确率进一步提高。

    Decoding device, decoding method, and signal transmission system

    公开(公告)号:US10447300B2

    公开(公告)日:2019-10-15

    申请号:US15951182

    申请日:2018-04-12

    Abstract: Embodiments of the present application provide a decoding method and a decoding device. The decoding device receives a second code word, which is transmitted from an encoding device based on a first code word. The first code word is generated by the encoding device based on a first encoded data sequence. After determining that a second encoded data sequence based on the second code word is not a correct replica of the first encoded data sequence, the decoding device performs a series of code element update processes to determining the correct replica of the first encoded data sequence.

    Data processing method and system based on quasi-cyclic LDPC

    公开(公告)号:US10355711B2

    公开(公告)日:2019-07-16

    申请号:US15638014

    申请日:2017-06-29

    Abstract: A data processing method based on a quasi-cyclic LDPC includes: when a size of service data is less than a magnitude of information bit of the quasi-cyclic LDPC, calculating a difference value between the magnitude of the information bit of the quasi-cyclic LDPC and the size of the service data, and filling the service data with the same amount of known data as the difference value (S103); coding the filled service data to obtain redundancy check data corresponding to the service data (S104); and sending the service data and the redundancy check data to a corresponding physical location in the storage unit (S105). It ensures that when a code length of the quasi-cyclic LDPC is constant, the code length ideally adapts to internal space of the storage unit, and the quasi-cyclic LDPC has a relatively high error correction capability, thereby improving reliability and service life of the storage unit.

    METHOD FOR RECOVERING A SPARSE COMMUNICATION SIGNAL FROM A RECEIVE SIGNAL
    6.
    发明申请
    METHOD FOR RECOVERING A SPARSE COMMUNICATION SIGNAL FROM A RECEIVE SIGNAL 有权
    从接收信号中恢复小数通信信号的方法

    公开(公告)号:US20160248611A1

    公开(公告)日:2016-08-25

    申请号:US15142731

    申请日:2016-04-29

    CPC classification number: H04L25/03987 H04B17/20

    Abstract: The patent application relates to a method for recovering a sparse communication signal from a receive signal, the receive signal being a channel output version of the sparse communication signal, the channel comprising channel coefficients being arranged to form a channel matrix, the method comprising determining a support set indicating a set of first indices of non-zero communication signal coefficients from the channel matrix and the receive signal, determining an estimate of the sparse communication signal upon the basis of the support set, the channel matrix and the receive signal, determining second indices of communication signal coefficients which are not indicated by the support set, and determining the sparse communication signal upon the basis of the support set, the estimate of the sparse communication signal, the second indices and the channel matrix.

    Abstract translation: 该专利申请涉及一种从接收信号中恢复稀疏通信信号的方法,该接收信号是稀疏通信信号的信道输出版本,该信道包括信道系数被布置以形成信道矩阵,该方法包括: 支持集合,其指示来自信道矩阵和接收信号的一组非零通信信号系数的第一索引,基于支持集合确定稀疏通信信号的估计,信道矩阵和接收信号,确定第二 未被支持集指示的通信信号系数的索引,以及基于支持集确定稀疏通信信号,稀疏通信信号的估计,第二索引和信道矩阵。

    CODE MODULATION AND DEMODULATION METHOD AND APPARATUS FOR HIGH ORDER MODULATION

    公开(公告)号:US20150078486A1

    公开(公告)日:2015-03-19

    申请号:US14551876

    申请日:2014-11-24

    CPC classification number: H04L27/361 H04L1/0057 H04L1/007 H04L27/38

    Abstract: Disclosed are a code modulation method and apparatus for high order modulation. The method comprises: converting information that needs to be transmitted into a bit data stream, and demultiplexing the bit data stream into more than one channel of bit data stream; performing first-type coding on at least one channel of bit data stream in the more than one channel of stream, to obtain first output data; performing second-type coding on at least one channel of the remaining channels of bit data stream on which the first-type coding is not performed, to obtain second output data; and performing quadrature amplitude modulation on the first output data, to generate a modulation symbol for output. Compared with the prior art, the correctness rate of demodulation in the technical solution is improved significantly, achieving higher transmission efficiency.

    Abstract translation: 公开了一种用于高阶调制的码调制方法和装置。 该方法包括:将需要发送的信息转换成比特数据流,以及将比特数据流多路分解成多于一个信道的比特数据流; 在流的多于一个信道中的位数据流的至少一个信道上执行第一类型编码,以获得第一输出数据; 对未执行第一类型编码的比特数据流的剩余信道的至少一个信道执行第二类型编码,以获得第二输出数据; 并对第一输出数据执行正交幅度调制,以产生用于输出的调制符号。 与现有技术相比,技术解决方案的正确率明显提高,传输效率更高。

    VIDEO CODING METHOD, APPARATUS, AND DEVICE, AND MEDIUM

    公开(公告)号:US20230239474A1

    公开(公告)日:2023-07-27

    申请号:US18192553

    申请日:2023-03-29

    CPC classification number: H04N19/124 H04N19/107

    Abstract: This disclosure relates to a video compression method, apparatus, and device, and a medium. The method includes: obtaining a video frame, where the video frame includes a first dynamic group of pictures and a second dynamic group of pictures; extracting a first I frame in the first dynamic group of pictures, and extracting a second I frame in the second dynamic group of pictures; deleting duplicate data between the first I frame and the second I frame, to obtain a target I frame; and compressing the target I frame. The duplicate data between the first I frame and the second I frame is deleted, and this does not affect integrity of data of the video frame.

    Flash memory error correction method and apparatus

    公开(公告)号:US10691535B2

    公开(公告)日:2020-06-23

    申请号:US15965424

    申请日:2018-04-27

    Abstract: A flash memory error correction method and apparatus is provided. The method includes determining a first data bit in a flash memory page, where the first data bit corresponds to different data respectively in the data obtained by reading the flash memory page using the (n+1)th read voltage threshold and the data obtained by reading the flash memory page using the mth read voltage threshold; and then reducing a confidence level of the first data bit in the data obtained by reading the flash memory page using the (n+1)th read voltage threshold; and performing, according to an adjusted confidence level of the first data bit, error correction decoding on the data obtained by reading the flash memory page using the (n+1)th read voltage threshold. Present disclosure effectively improves a success rate of error correction decoding, thereby significantly improving performance of an SSD storage system.

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