Abstract:
Embodiments of the present application provide a decoding method and a decoding device. The decoding device receives a second code word, which is transmitted from an encoding device based on a first code word. The first code word is generated by the encoding device based on a first encoded data sequence. After determining that a second encoded data sequence based on the second code word is not a correct replica of the first encoded data sequence, the decoding device performs a series of code element update processes to determining the correct replica of the first encoded data sequence.
Abstract:
A data processing method based on a quasi-cyclic LDPC includes: when a size of service data is less than a magnitude of information bit of the quasi-cyclic LDPC, calculating a difference value between the magnitude of the information bit of the quasi-cyclic LDPC and the size of the service data, and filling the service data with the same amount of known data as the difference value (S103); coding the filled service data to obtain redundancy check data corresponding to the service data (S104); and sending the service data and the redundancy check data to a corresponding physical location in the storage unit (S105). It ensures that when a code length of the quasi-cyclic LDPC is constant, the code length ideally adapts to internal space of the storage unit, and the quasi-cyclic LDPC has a relatively high error correction capability, thereby improving reliability and service life of the storage unit.
Abstract:
A high order modulation method, a demapping method, and a corresponding device are provided. With the high order modulation method, important bits is distinguished, and the important bits are divided into important bits for distinguishing large regions and important bits for distinguishing small regions according to the difficulty of judgment areas. Therefore, the judgment accuracy rate of a demodulator is further improved.
Abstract:
Embodiments of the present application provide a decoding method and a decoding device. The decoding device receives a second code word, which is transmitted from an encoding device based on a first code word. The first code word is generated by the encoding device based on a first encoded data sequence. After determining that a second encoded data sequence based on the second code word is not a correct replica of the first encoded data sequence, the decoding device performs a series of code element update processes to determining the correct replica of the first encoded data sequence.
Abstract:
A data processing method based on a quasi-cyclic LDPC includes: when a size of service data is less than a magnitude of information bit of the quasi-cyclic LDPC, calculating a difference value between the magnitude of the information bit of the quasi-cyclic LDPC and the size of the service data, and filling the service data with the same amount of known data as the difference value (S103); coding the filled service data to obtain redundancy check data corresponding to the service data (S104); and sending the service data and the redundancy check data to a corresponding physical location in the storage unit (S105). It ensures that when a code length of the quasi-cyclic LDPC is constant, the code length ideally adapts to internal space of the storage unit, and the quasi-cyclic LDPC has a relatively high error correction capability, thereby improving reliability and service life of the storage unit.
Abstract:
The patent application relates to a method for recovering a sparse communication signal from a receive signal, the receive signal being a channel output version of the sparse communication signal, the channel comprising channel coefficients being arranged to form a channel matrix, the method comprising determining a support set indicating a set of first indices of non-zero communication signal coefficients from the channel matrix and the receive signal, determining an estimate of the sparse communication signal upon the basis of the support set, the channel matrix and the receive signal, determining second indices of communication signal coefficients which are not indicated by the support set, and determining the sparse communication signal upon the basis of the support set, the estimate of the sparse communication signal, the second indices and the channel matrix.
Abstract:
Disclosed are a code modulation method and apparatus for high order modulation. The method comprises: converting information that needs to be transmitted into a bit data stream, and demultiplexing the bit data stream into more than one channel of bit data stream; performing first-type coding on at least one channel of bit data stream in the more than one channel of stream, to obtain first output data; performing second-type coding on at least one channel of the remaining channels of bit data stream on which the first-type coding is not performed, to obtain second output data; and performing quadrature amplitude modulation on the first output data, to generate a modulation symbol for output. Compared with the prior art, the correctness rate of demodulation in the technical solution is improved significantly, achieving higher transmission efficiency.
Abstract:
This disclosure relates to a video compression method, apparatus, and device, and a medium. The method includes: obtaining a video frame, where the video frame includes a first dynamic group of pictures and a second dynamic group of pictures; extracting a first I frame in the first dynamic group of pictures, and extracting a second I frame in the second dynamic group of pictures; deleting duplicate data between the first I frame and the second I frame, to obtain a target I frame; and compressing the target I frame. The duplicate data between the first I frame and the second I frame is deleted, and this does not affect integrity of data of the video frame.
Abstract:
A flash memory error correction method and apparatus is provided. The method includes determining a first data bit in a flash memory page, where the first data bit corresponds to different data respectively in the data obtained by reading the flash memory page using the (n+1)th read voltage threshold and the data obtained by reading the flash memory page using the mth read voltage threshold; and then reducing a confidence level of the first data bit in the data obtained by reading the flash memory page using the (n+1)th read voltage threshold; and performing, according to an adjusted confidence level of the first data bit, error correction decoding on the data obtained by reading the flash memory page using the (n+1)th read voltage threshold. Present disclosure effectively improves a success rate of error correction decoding, thereby significantly improving performance of an SSD storage system.
Abstract:
This application discloses a storage controller. When running, the storage controller encodes, according to a check matrix, K to-be-coded data chunks obtained from a client, to generate two check chunks. In this way, if any chunk is damaged subsequently, the damaged chunk may be recovered by using the check matrix and an undamaged chunk.