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    Node controller and method for responding to request based on node controller
    2.
    发明授权
    Node controller and method for responding to request based on node controller 有权

    公开(公告)号：US10324646B2

    公开(公告)日：2019-06-18

    申请号：US15066623

    申请日：2016-03-10

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Gongyi Wang ,  Ben Chen ,  Yafei Zhao

    IPC: G06F3/06 ,  G06F9/54 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/0831

    Abstract: A node controller-based request responding method and node controller, where the method includes receiving, by a first node controller, a first packet, acquiring an information directory, and querying, in the information directory, whether a memory address requested by the first packet is occupied by a second node controller, and when the memory address requested by the first packet is occupied by the second node controller, querying node presence information to determine whether the second node controller exists, and when it is determined that the second node controller does not exist, generating and sending an invalid response packet.

    Node Controller and Method for Responding to Request Based on Node Controller
    6.
    发明申请
    Node Controller and Method for Responding to Request Based on Node Controller 审中-公开
    节点控制器和基于节点控制器的请求响应方法

    公开(公告)号：US20160196087A1

    公开(公告)日：2016-07-07

    申请号：US15066623

    申请日：2016-03-10

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Gongyi Wang ,  Ben Chen ,  Yafei Zhao

    IPC: G06F3/06

    CPC classification number: G06F3/0638 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/54 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/0831 ,  G06F2212/1048

    Abstract: A node controller-based request responding method and node controller, where the method includes receiving, by a first node controller, a first packet, acquiring an information directory, and querying, in the information directory, whether a memory address requested by the first packet is occupied by a second node controller, and when the memory address requested by the first packet is occupied by the second node controller, querying node presence information to determine whether the second node controller exists, and when it is determined that the second node controller does not exist, generating and sending an invalid response packet.

    Abstract translation: 一种基于节点控制器的请求响应方法和节点控制器，其中所述方法包括由第一节点控制器接收第一分组，获取信息目录，以及在所述信息目录中查询由所述第一分组请求的存储器地址 被第二节点控制器占用，并且当由第一分组请求的存储器地址被第二节点控制器占用时，查询节点存在信息以确定第二节点控制器是否存在，以及何时确定第二节点控制器执行 不存在，生成和发送无效的响应数据包。

    Storage Expansion Apparatus and Server
    7.
    发明申请
    Storage Expansion Apparatus and Server 有权
    存储扩展设备和服务器

    公开(公告)号：US20150032932A1

    公开(公告)日：2015-01-29

    申请号：US14512790

    申请日：2014-10-13

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Sheng Chang ,  Gongyi Wang ,  Tao Li

    IPC: G06F13/42 ,  G06F13/16 ,  G06F13/28

    CPC classification number: G06F13/4282 ,  G06F13/00 ,  G06F13/1689 ,  G06F13/28 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027

    Abstract: A storage expansion apparatus and a server, where the storage expansion apparatus includes a quick path interconnect (QPI) interface module, which communicates with a central processing unit (CPU) through a QPI bus; a peripheral component interconnect express (PCIe) interface module, which communicates with the CPU through a PCIe bus; an interface selecting module, connected to the QPI interface module and the PCIe interface module separately; a home agent (HA) module, connected to the interface selecting module; and a memory controller engine (MCEng) module, connected to the HA module and the interface selecting module separately. The storage expansion apparatus may serve as a CPU memory capacity expansion device, and may also serve as storage expansion hardware of storage input and output (TO).

    Abstract translation: 一种存储扩展装置和服务器，其中存储扩展装置包括通过QPI总线与中央处理单元（CPU）通信的快速路径互连（QPI）接口模块; 外围组件互连快速（PCIe）接口模块，其通过PCIe总线与CPU通信; 接口选择模块，分别连接到QPI接口模块和PCIe接口模块; 连接到接口选择模块的归属代理（HA）模块; 以及分别连接到HA模块和接口选择模块的存储器控​​制器引擎（MCEng）模块。 存储扩展装置可以用作CPU存储器容量扩展装置，并且还可以用作存储输入和输出（TO）的存储扩展硬件。

    Flash memory error correction method and apparatus
    9.
    发明授权
    Flash memory error correction method and apparatus 有权

    公开(公告)号：US10691535B2

    公开(公告)日：2020-06-23

    申请号：US15965424

    申请日：2018-04-27

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Yanxing Zeng ,  Jianqiang Shen ,  Gongyi Wang

    IPC: G06F11/00 ,  G06F11/10 ,  G11C29/42 ,  G11C11/56 ,  G06F3/06 ,  G11C16/26 ,  G11C16/34 ,  G11C29/52 ,  H03M13/25

    Abstract: A flash memory error correction method and apparatus is provided. The method includes determining a first data bit in a flash memory page, where the first data bit corresponds to different data respectively in the data obtained by reading the flash memory page using the (n+1)th read voltage threshold and the data obtained by reading the flash memory page using the mth read voltage threshold; and then reducing a confidence level of the first data bit in the data obtained by reading the flash memory page using the (n+1)th read voltage threshold; and performing, according to an adjusted confidence level of the first data bit, error correction decoding on the data obtained by reading the flash memory page using the (n+1)th read voltage threshold. Present disclosure effectively improves a success rate of error correction decoding, thereby significantly improving performance of an SSD storage system.

    Encoding method and apparatus
    10.
    发明授权
    Encoding method and apparatus 有权

    公开(公告)号：US10305512B2

    公开(公告)日：2019-05-28

    申请号：US15924007

    申请日：2018-03-16

    Applicant: HUAWEI TECHNOLOGIES, CO., LTD.

    Inventor： Kun Guan ,  Jinan Leng ,  Gongyi Wang ,  Shaohui Quan ,  Jianqiang Shen

    IPC: H03M7/30 ,  G06F17/30

    Abstract: An encoding method and apparatus is described. In an encoding method, when a first target sub-block in a target block is obtained, a hash operation is first performed on the first target sub-block. Then, a first hash table is queried for a corresponding hash value according to an operation result, and a corresponding location in a reference block is found according to the hash value obtained by means of query, that is, first reference data is found. The first piece of target data in the first target sub-block is matched with the first reference data, and second target data in the target block is matched with second reference data in the reference block. In this way, an approximate location is predetermined, so that a range in which matching needs to be performed is narrowed, a data compression time is reduced, and data compression efficiency is improved.

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