公开(公告)号：US20220077105A1

公开(公告)日：2022-03-10

申请号：US17525964

申请日：2021-11-15

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Ran He ,  Huifang Jiao ,  Yufeng Dai ,  Guanglin Yang ,  Chihon Ho ,  Ronghua Xie

IPC: H01L23/00

Abstract: Embodiments of this application disclose a hybrid bonding structure and a hybrid bonding method. The hybrid bonding structure includes a first chip and a second chip. A surface of the first chip includes a first insulation dielectric and a first metal, and a first gap area exists between the first metal and the first insulation dielectric. A surface of the second chip includes a second insulation dielectric and a second metal. A surface of the first metal is higher than a surface of the first insulation dielectric. Metallic bonding is formed after the first metal is in contact with the second metal, and the first metal is longitudinally and transversely deformed in the first gap area. Insulation dielectric bonding is formed after the first insulation dielectric is in contact with the second insulation dielectric.

公开(公告)号：US20240178167A1

公开(公告)日：2024-05-30

申请号：US18437444

申请日：2024-02-09

Applicant: Huawei Technologies Co., Ltd.

Inventor： Ran He ,  Huifang Jiao

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/03845 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05582 ,  H01L2224/05584 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/80357 ,  H01L2224/80896 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059

Abstract: The invention provide a chip package structure, which includes a first chip and a first hybrid bonding structure. The first chip is connected to another chip through the first hybrid bonding structure. The first hybrid bonding structure includes a first bonding layer. The first bonding layer is disposed on a side away from a substrate of the first chip, and the first bonding layer includes a first insulation material and a plurality of first metal solder pads embedded in the first insulation material. Each of the plurality of first metal solder pads includes a groove structure. A groove bottom of the groove structure is buried in the first insulation material, and a groove opening of the groove structure is exposed to a surface of the first insulation material and is flush with the surface of the first insulation material.

公开(公告)号：US11756922B2

公开(公告)日：2023-09-12

申请号：US17525964

申请日：2021-11-15

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ran He ,  Huifang Jiao ,  Yufeng Dai ,  Guanglin Yang ,  Chihon Ho ,  Ronghua Xie

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L2224/0801 ,  H01L2224/08056 ,  H01L2224/08059 ,  H01L2224/08145 ,  H01L2224/80047 ,  H01L2224/80095 ,  H01L2224/80345 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of this application disclose a hybrid bonding structure and a hybrid bonding method. The hybrid bonding structure includes a first chip and a second chip. A surface of the first chip includes a first insulation dielectric and a first metal, and a first gap area exists between the first metal and the first insulation dielectric. A surface of the second chip includes a second insulation dielectric and a second metal. A surface of the first metal is higher than a surface of the first insulation dielectric. Metallic bonding is formed after the first metal is in contact with the second metal, and the first metal is longitudinally and transversely deformed in the first gap area. Insulation dielectric bonding is formed after the first insulation dielectric is in contact with the second insulation dielectric.

公开(公告)号：US20250054888A1

公开(公告)日：2025-02-13

申请号：US18930837

申请日：2024-10-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ran He

IPC: H01L23/00

Abstract: An integrated circuit includes a substrate, an electronic component, a wiring layer, a dielectric bonding layer, a connection pattern, and a barrier layer. The wiring layer is disposed on the substrate, and is electrically connected to the electronic component. The wiring layer includes a metal trace. The dielectric bonding layer is disposed on a side that is of the wiring layer and that is away from the substrate. The connection pattern runs through the dielectric bonding layer, and is electrically connected to the metal trace. The connection pattern includes a seed layer and a conductive block that are stacked, and the seed layer is located on a side that is of the conductive block and that is close to the substrate. The barrier layer is disposed between the conductive block and the dielectric bonding layer, and surrounds a side surface of the conductive block.

公开(公告)号：US12183425B2

公开(公告)日：2024-12-31

申请号：US17893067

申请日：2022-08-22

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Huifang Jiao ,  Ran He ,  Luming Fan ,  Yue Pan

IPC: G11C7/12 ,  G11C7/06 ,  G11C7/10 ,  G11C8/08

Abstract: A memory includes S storage blocks, N global bitlines, and a signal amplification circuit. Each of the S storage blocks is connected to the N global bitlines, the N global bitlines are connected to the signal amplification circuit, the signal amplification circuit is configured to amplify electrical signals on the N global bitlines, and each storage block includes N columns of storage units, N local bitlines, and N bitline switches. In each storage block, storage units in an ith column are connected to an ith local bitline, the ith local bitline is connected to an ith global bitline by using an ith bitline switch in the N bitline switches. A memory array is fine-grained, so that ith local bitlines in the S storage blocks can share one global bitline.

公开(公告)号：US20230070633A1

公开(公告)日：2023-03-09

申请号：US18050030

申请日：2022-10-26

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ran He ,  Shan Gao

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: An integrated circuit includes: a silicon substrate, and a redistribution layer located on the silicon substrate, where the redistribution layer includes metal routing and a dielectric layer of a first material. An isolation area that runs through the redistribution layer is disposed in the redistribution layer. The isolation area includes a second material. A porosity of the second material is less than a porosity of the first material. A via is disposed inside the isolation area, and the second material surrounds a part of the via. The second material may be a dense material, such that water vapor in the via can be effectively isolated.

公开(公告)号：US11232286B2

公开(公告)日：2022-01-25

申请号：US17038208

申请日：2020-09-30

Applicant: Huawei Technologies Co., Ltd. ,  Institute of Automation, Chinese Academy of Sciences

Inventor： Qiang Rao ,  Bing Yu ,  Bailan Feng ,  Yibo Hu ,  Xiang Wu ,  Ran He ,  Zhenan Sun

IPC: G06K9/00 ,  G06K9/62 ,  G06T5/00 ,  G06T9/00

Abstract: A method and an apparatus for generating a face rotation image are provided. The method includes: performing pose encoding on an obtained face image based on two or more landmarks in the face image, to obtain pose encoded images; obtaining a plurality of training images each including a face from a training data set, wherein presented rotation angles of the faces included in the plurality of training images are the same; performing pose encoding on a target face image based on two or more landmarks in the target face image in the foregoing similar manner, to obtain pose encoded images, wherein the target face image is obtained based on the plurality of training images; generating a to-be-input signal based on the face image and the foregoing two types of pose encoded images; and inputting the to-be-input signal into an face rotation image generative model to obtain a face rotation image.