公开(公告)号：US20160087096A1

公开(公告)日：2016-03-24

申请号：US14495508

申请日：2014-09-24

Applicant: HONGNING YANG ,  XIN LIN ,  ZHIHONG ZHANG ,  JIANG-KAI ZUO

Inventor： HONGNING YANG ,  XIN LIN ,  ZHIHONG ZHANG ,  JIANG-KAI ZUO

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7824 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835 ,  H01L29/78624

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first region of semiconductor material having a first conductivity type and a first dopant concentration, a second region of semiconductor material having a second conductivity type overlying the first region, a drift region of semiconductor material having the first conductivity type overlying the second region, and a drain region of semiconductor material having the first conductivity type. The drift region and the drain region are electrically connected, with at least a portion of the drift region residing between the drain region and the second region, and at least a portion of the second region residing between that drift region and the first region. In one or more exemplary embodiments, the first region abuts an underlying insulating layer of dielectric material.

Abstract translation: 提供半导体器件结构和相关的制造方法。 示例性的半导体器件结构包括具有第一导电类型和第一掺杂剂浓度的第一半导体材料区域，具有覆盖第一区域的第二导电类型的第二半导体材料区域，具有第一导电类型的半导体材料的漂移区域 覆盖第二区域，以及具有第一导电类型的半导体材料的漏极区域。 漂移区域和漏极区域电连接，漂移区域的至少一部分位于漏极区域和第二区域之间，并且第二区域的至少一部分位于该漂移区域和第一区域之间。 在一个或多个示例性实施例中，第一区域邻接介电材料的下层绝缘层。

公开(公告)号：US20130175616A1

公开(公告)日：2013-07-11

申请号：US13781722

申请日：2013-02-28

Applicant: WON GI MIN ,  ZHIHONG ZHANG ,  HONGZHONG XU ,  JIANG-KAI ZUO

Inventor： WON GI MIN ,  ZHIHONG ZHANG ,  HONGZHONG XU ,  JIANG-KAI ZUO

IPC: H01L29/78

CPC classification number: H01L29/7823 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.

公开(公告)号：US20120012970A1

公开(公告)日：2012-01-19

申请号：US12835900

申请日：2010-07-14

Applicant: HONGZHONG XU ,  ZHIHONG ZHANG ,  JIANG-KAI ZUO

Inventor： HONGZHONG XU ,  ZHIHONG ZHANG ,  JIANG-KAI ZUO

IPC: H01L27/07 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/94 ,  H01L29/66181

Abstract: A semiconductor device includes an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device; a capacitor dielectric on the isolated p-type well; a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device; a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode; a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, wherein a portion of the isolated p-type well between the first and second p-type contact regions is under the p-type polysilicon electrode and the capacitor dielectric; and an n-type isolation region surrounding the isolated p-type well. This device may be conveniently coupled to a fringe capacitor.

Abstract translation: 半导体器件包括隔离的p型阱，其中隔离的p型阱是电容器器件的第一电极; 隔离p型阱上的电容器电介质; 电容器电介质上的p型多晶硅电极，其中p型多晶硅电极是电容器器件的第二电极; 分离的p型阱中的第一p型接触区，从p型多晶硅电极的第一侧壁横向延伸; 在隔离的p型阱中的第二p型接触区域，从p型多晶硅电极的第二侧壁横向延伸，与p型多晶硅电极的第一侧壁相对，其中一部分隔离的p型 第一和第二p型接触区之间的阱在p型多晶硅电极和电容器电介质之下; 以及围绕隔离p型阱的n型隔离区。 该装置可以方便地连接到边缘电容器。