公开(公告)号：US20160087096A1

公开(公告)日：2016-03-24

申请号：US14495508

申请日：2014-09-24

Applicant: HONGNING YANG ,  XIN LIN ,  ZHIHONG ZHANG ,  JIANG-KAI ZUO

Inventor： HONGNING YANG ,  XIN LIN ,  ZHIHONG ZHANG ,  JIANG-KAI ZUO

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7824 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835 ,  H01L29/78624

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first region of semiconductor material having a first conductivity type and a first dopant concentration, a second region of semiconductor material having a second conductivity type overlying the first region, a drift region of semiconductor material having the first conductivity type overlying the second region, and a drain region of semiconductor material having the first conductivity type. The drift region and the drain region are electrically connected, with at least a portion of the drift region residing between the drain region and the second region, and at least a portion of the second region residing between that drift region and the first region. In one or more exemplary embodiments, the first region abuts an underlying insulating layer of dielectric material.

Abstract translation: 提供半导体器件结构和相关的制造方法。 示例性的半导体器件结构包括具有第一导电类型和第一掺杂剂浓度的第一半导体材料区域，具有覆盖第一区域的第二导电类型的第二半导体材料区域，具有第一导电类型的半导体材料的漂移区域 覆盖第二区域，以及具有第一导电类型的半导体材料的漏极区域。 漂移区域和漏极区域电连接，漂移区域的至少一部分位于漏极区域和第二区域之间，并且第二区域的至少一部分位于该漂移区域和第一区域之间。 在一个或多个示例性实施例中，第一区域邻接介电材料的下层绝缘层。

公开(公告)号：US20140134820A1

公开(公告)日：2014-05-15

申请号：US14157317

申请日：2014-01-16

Applicant: XIN LIN ,  DANIEL J. BLOMBERG ,  HONGNING YANG ,  JIANG-KAI ZUO

Inventor： XIN LIN ,  DANIEL J. BLOMBERG ,  HONGNING YANG ,  JIANG-KAI ZUO

IPC: H01L29/66

CPC classification number: H01L29/6625 ,  H01L21/82285 ,  H01L27/0826 ,  H01L29/735

Abstract: Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface.

Abstract translation: 通过提供与晶体管表面上的发射极相同的导电类型的另外的掺杂区域，可以减少或消除具有延伸到发射极和基极接触之间的晶体管表面的基极的一部分的双极晶体管中的不稳定性和漂移 在发射极和基极之间。 另外的区域期望比表面上的基极区域重掺杂，并且比相邻的发射极更重掺杂。 在另一个实施例中，与发射器相同的导电类型的仍然还是另外的区域被提供在另外的区域和发射极之间或者在发射极内侧。 仍然还是进一步的区域期望比其他区域更重掺杂。 这样的另外的区域屏蔽近表面碱基区域可能存在于覆盖晶体管表面的电介质层或界面中的俘获电荷。

公开(公告)号：US20140206168A1

公开(公告)日：2014-07-24

申请号：US14071344

申请日：2013-11-04

Applicant: Hongning Yang ,  XIN LIN ,  JIANG-KAI ZUO

Inventor： Hongning Yang ,  XIN LIN ,  JIANG-KAI ZUO

IPC: H01L29/66

CPC classification number: H01L29/66681 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7801 ,  H01L29/7816

Abstract: Adverse tradeoff between BVDSS and Rdson in LDMOS devices employing a drift space adjacent the drain, is avoided by providing a lightly doped region of a first conductivity type (CT) separating the first CT drift space from an opposite CT WELL region in which the first CT source is located, and a further region of the opposite CT (e.g., formed by an angled implant) extending through part of the WELL region under an edge of the gate located near a boundary of the WELL region into the lightly doped region, and a shallow still further region of the first CT Ohmically coupled to the source and ending near the gate edge whereby the effective channel length in the further region is reduced to near zero. Substantial improvement in BVDSS and/or Rdson can be obtained without degrading the other or significant adverse affect on other device properties.

Abstract translation: 通过提供将第一CT漂移空间与相对的CT WELL区域分开的第一导电类型（CT）的轻掺杂区域来避免采用邻近漏极的漂移空间的LDMOS器件中的BVDSS和Rdson之间的不利权衡，其中第一CT 源和位于WELL区附近的位于边缘边缘的WELL区域的一部分延伸穿入部分WELL区域的另一区域（例如由成角度的植入物形成）进入轻掺杂区域，以及 第一CT的较浅的另一区域欧姆耦合到源极并且在栅极边缘附近结束，由此在另一区域中的有效沟道长度减小到接近零。 可以获得BVDSS和/或Rdson的显着改善，而不会降低对其他设备性能的其他影响或显着的不利影响。

公开(公告)号：US20140235025A1

公开(公告)日：2014-08-21

申请号：US14261231

申请日：2014-04-24

Applicant: HONGNING YANG ,  XIN LIN ,  JIANG-KAI ZUO

Inventor： HONGNING YANG ,  XIN LIN ,  JIANG-KAI ZUO

IPC: H01L29/66

CPC classification number: H01L29/66719 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7809 ,  H01L29/7812

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first vertical drift region of semiconductor material, a second vertical drift region of semiconductor material, and a buried lateral drift region of semiconductor material that abuts the vertical drift regions. In one or more embodiments, the vertical drift regions and buried lateral drift region have the same conductivity type, wherein a body region of the opposite conductivity type overlies the buried lateral drift region between the vertical drift regions.

Abstract translation: 提供半导体器件结构和相关的制造方法。 示例性的半导体器件结构包括半导体材料的第一垂直漂移区域，半导体材料的第二垂直漂移区域和邻接垂直漂移区域的半导体材料的埋入横向漂移区域。 在一个或多个实施例中，垂直漂移区域和掩埋横向漂移区域具有相同的导电类型，其中相反导电类型的体区域覆盖垂直漂移区域之间的埋入横向漂移区域。

公开(公告)号：US20140363945A1

公开(公告)日：2014-12-11

申请号：US14466042

申请日：2014-08-22

Applicant: XIN LIN ,  DANIEL J. BLOMBERG ,  JIANG-KAI ZUO

Inventor： XIN LIN ,  DANIEL J. BLOMBERG ,  JIANG-KAI ZUO

IPC: H01L29/66 ,  H01L21/74

CPC classification number: H01L29/6625 ,  H01L21/74 ,  H01L29/0821 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/735

Abstract: Bipolar transistors and methods for fabricating bipolar transistors are provided. In one embodiment, the method includes the step or process of providing a substrate having therein a semiconductor base region of a first conductivity type and first doping density proximate an upper substrate surface. A multilevel collector structure of a second opposite conductivity type is formed in the base region. The multilevel collector includes a first collector part extending to a collector contact, a second collector part Ohmically coupled to the first collector part underlying the upper substrate surface by a first depth, a third collector part laterally spaced apart from the second collector part and underlying the upper substrate surface by a second depth and having a first vertical thickness, and a fourth collector part Ohmically coupling the second and third collector parts and having a second vertical thickness different than the first vertical thickness.

Abstract translation: 提供双极晶体管和制造双极晶体管的方法。 在一个实施例中，该方法包括提供其中具有第一导电类型的半导体基区和靠近上衬底表面的第一掺杂密度的衬底的步骤或工艺。 第二相反导电类型的多电平集电器结构形成在基极区域中。 所述多级集电器包括延伸到集电极触点的第一集电器部分，第二集电器部分，所述第二集电器部分以欧姆方式耦合到所述上基板表面下方的第一集电器部分第一深度;第三集电器部分，其与所述第二集电器部分横向间隔开， 上部衬底表面具有第二深度并具有第一垂直厚度;以及第四集电器部分，其将所述第二和第三集电器部分欧姆耦合并且具有不同于所述第一垂直厚度的第二垂直厚度。

公开(公告)号：US20120264270A1

公开(公告)日：2012-10-18

申请号：US13534971

申请日：2012-06-27

Applicant: XIN LIN ,  Daniel J. Blomberg ,  Jiang-Kai Zou

Inventor： XIN LIN ,  Daniel J. Blomberg ,  Jiang-Kai Zou

IPC: H01L21/331

CPC classification number: H01L29/66272 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/7322

Abstract: Embodiments for forming improved bipolar transistors are provided, manufacturable by a CMOS IC process. The improved transistor comprises an emitter having first and second portions of different depths, a base underlying the emitter having a central portion of a first base width underlying the first portion of the emitter, a peripheral portion having a second base width larger than the first base width partly underlying the second portion of the emitter, and a transition zone of a third base width and lateral extent lying laterally between the first and second portions of the base, and a collector underlying the base. The gain of the transistor is larger than a conventional bipolar transistor made using the same CMOS process. By adjusting the lateral extent of the transition zone, the properties of the improved transistor can be tailored to suit different applications without modifying the underlying CMOS IC process.

Abstract translation: 提供用于形成改进的双极晶体管的实施例，可通过CMOS IC工艺制造。 改进的晶体管包括具有不同深度的第一和第二部分的发射器，发射器下面的基底具有位于发射器的第一部分下方的第一基底宽度的中心部分，具有大于第一基底的第二基底宽度的周边部分 部分位于发射体的第二部分下方的宽度，以及位于基底的第一和第二部分之间横向置换的第三基底宽度和横向范围的过渡区，以及位于基底的收集器。 晶体管的增益大于使用相同CMOS工艺制造的常规双极晶体管。 通过调整过渡区域的横向范围，可以调整改进晶体管的性能以适应不同的应用，而无需修改底层的CMOS IC工艺。

公开(公告)号：US20150162417A1

公开(公告)日：2015-06-11

申请号：US14098194

申请日：2013-12-05

Applicant: WEIZE CHEN ,  XIN LIN ,  PATRICE M. PARRIS

Inventor： WEIZE CHEN ,  XIN LIN ,  PATRICE M. PARRIS

IPC: H01L29/66 ,  H01L29/866

CPC classification number: H01L29/866 ,  H01L21/76224 ,  H01L29/0611 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/08 ,  H01L29/66106

Abstract: Zener diode structures and related fabrication methods and semiconductor devices are provided. An exemplary semiconductor device includes first and second Zener diode structures. The first Zener diode structure includes a first region, a second region that is adjacent to the first region, and a third region adjacent to the first region and the second region to provide a junction that is configured to influence a first reverse breakdown voltage of a junction between the first region and the second region. The second Zener diode structure includes a fourth region, a fifth region that is adjacent to the fourth region, and a sixth region adjacent to the fourth region and the fifth region to provide a junction configured to influence a second reverse breakdown voltage of a junction between the fourth region and the fifth region, wherein the second reverse breakdown voltage and the first reverse breakdown voltage are different.

Abstract translation: 提供齐纳二极管结构及相关制造方法和半导体器件。 示例性半导体器件包括第一和第二齐纳二极管结构。 第一齐纳二极管结构包括第一区域，与第一区域相邻的第二区域，以及与第一区域和第二区域相邻的第三区域，以提供被配置为影响第一区域的第一反向击穿电压 第一区域和第二区域之间的连接处。 第二齐纳二极管结构包括第四区域，与第四区域相邻的第五区域以及与第四区域和第五区域相邻的第六区域，以提供被配置为影响第二区域的第二反向击穿电压 第四区域和第五区域，其中第二反向击穿电压和第一反向击穿电压不同。