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公开(公告)号：US11960771B2
公开(公告)日：2024-04-16
申请号：US17900968
申请日：2022-09-01
Applicant: Hitachi, Ltd.
Inventor： Shugo Ogawa , Ryosuke Tatsumi , Yoshinori Ohira , Hiroto Ebara , Junji Ogawa
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0647 , G06F3/0673
Abstract: A first controller manages first mapping information for accessing data stored in a storage area, management of which is assigned to the first controller, and second mapping information for accessing data stored in a predetermined storage area, management of which is assigned to a second controller. The second controller, when having executed garbage collection on the predetermined storage area, changes mapping information to post-migration mapping information for accessing data after being migrated by the garbage collection. The first controller acquires the post-migration mapping information from the second controller, and updates the second mapping information using the post-migration mapping information when information in the second mapping information and is to be used for accessing the data in the predetermined storage area has been updated accompanying the garbage collection when the first controller accesses the data in the predetermined storage area after the garbage collection by using the second mapping information.
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公开(公告)号：US11068180B2
公开(公告)日：2021-07-20
申请号：US16564115
申请日：2019-09-09
Applicant: HITACHI, LTD.
Inventor： Yukihiro Yoshino , Junji Ogawa , Go Uehara
Abstract: A higher-level system that inputs and outputs data to/from a storage area including one or more logical areas respectively provided from one or more NVM drives manages the storage area, and manages a plurality of chunks that are a plurality of areas forming the storage area, each of the chunks being a unit of data input/output and being an non-overwritable area. Each of the plurality of chunks has the same chunk size, and each of the plurality of chunks includes a part of each of one or more logical areas. Each of the plurality of chunks includes, for each of the one or more NVM drives, all or part of one or more logical blocks that are one or more ranges corresponding to one or more physical blocks, respectively, but does not include at least a part of a logical block that is entirely or partially included in another chunk.
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公开(公告)号：US10915441B2
公开(公告)日：2021-02-09
申请号：US16495752
申请日：2017-08-23
Inventor： Koshi Hoshino , Shigeo Homma , Junji Ogawa , Yoshinori Ohira
IPC: G06F12/02 , G06F3/06 , G06F12/0868
Abstract: An upper system of an NVM device transmits, to the NVM device, a write command that designates a logical address, the write command being associated with an expiration date corresponding to a data expiration date correlated with write target data. The NVM device correlates an expiration date correlated with the write command with a logical address specified from the write command. The NVM device writes pieces of data of which the remaining time which is the time to an expiration date belongs to the same remaining time range to the same physical storage area among the plurality of physical storage areas. The NVM device erases data from a physical storage area when the expiration dates of all pieces of data in the physical storage area have expired.
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公开(公告)号：US10310770B2
公开(公告)日：2019-06-04
申请号：US15741600
申请日：2015-11-05
Applicant: Hitachi, Ltd.
Inventor： Masatsugu Oshimi , Junji Ogawa , Yoshihiro Oikawa
Abstract: This nonvolatile memory device has a blockwise-erase nonvolatile memory including a plurality of physical areas, and also has a memory controller which transmits one of a plurality of types of commands to the nonvolatile memory. After an erase command to erase one of the physical areas has been transmitted, but before a response to that erase command is received, the memory controller determines whether to suspend the ongoing erasure of the physical area, on the basis of whether there is a command to be transmitted and/or on the basis of the degree of deterioration of the physical area being erased. If the determination is affirmative, the memory controller transmits a command to the nonvolatile memory to suspend the erasure.
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公开(公告)号：US20150254016A1
公开(公告)日：2015-09-10
申请号：US14721608
申请日：2015-05-26
Applicant: Hitachi, Ltd.
Inventor： HIROAKI AKUTSU , Junji Ogawa
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0665 , G06F3/0689 , G06F11/1092 , G06F2003/0692
Abstract: Storage system comprises a second storage apparatus, which is coupled to multiple first storage apparatuses and is of a different type from the first storage apparatuses, and a first control device, which exists either inside or outside of the second storage apparatus. Row of stripes comprising multiple data elements obtained by segmenting a prescribed data unit, and a redundancy code for rebuilding the data elements, is distributively stored in multiple first storage apparatuses, which are more numerous than the total number of stripe data elements, which are either the data elements or redundancy code, in the row of stripes. The row of stripes is configured to enable the rebuilding of the stripe data elements even when a failure has occurred in up to a prescribed allowable number, which is two or more, of the first storage apparatuses storing the stripe data elements of the relevant row of stripes.
Abstract translation: 存储系统包括耦合到多个第一存储装置并且与第一存储装置不同的第二存储装置，以及存在于第二存储装置的内部或外部的第一控制装置。 包括通过分割规定数据单元获得的多个数据元素的条纹行和用于重建数据元素的冗余码被分布地存储在多个第一存储设备中，该多个第一存储设备比条带数据元素的总数多 数据元素或冗余码，在行条中。 这条条被配置为即使当发生故障时也能够重建条带数据元素，直到存储有关行的条带数据元素的第一存储装置中的两个或更多个规定的可允许数量 条纹。
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Patent Agency Ranking
公开(公告)号：US09111618B2
公开(公告)日：2015-08-18
申请号：US14329171
申请日：2014-07-11
Applicant: Hitachi, Ltd.
Inventor： Atsushi Kawamura , Junji Ogawa
CPC classification number: G11C16/0483 , G06F3/0608 , G06F3/0616 , G06F3/0641 , G06F3/0679 , G06F3/0688 , G06F11/1044 , G06F11/108 , G06F12/0246 , G06F2212/7202 , G11C16/04
Abstract: Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A flash memory module includes a plurality of flash memory chips and a memory controller. Each flash memory chip includes a plurality of blocks, each block including a plurality of physical pages, each physical page being a unit for writing/reading data. The memory controller is configured to manage a first set and a second set of user data and a guarantee code associated with the user data. If the first set and the second set of user data are the same, then the same data sets are stored in a first physical page and the first and second guarantee codes are stored in a second physical page.
Abstract translation: 通过使用与每个数据不同的代码分配的数据进行解除复制来提高数据容量效率。 闪存模块包括多个闪存芯片和存储器控制器。 每个闪速存储器芯片包括多个块，每个块包括多个物理页，每个物理页是用于写入/读取数据的单元。 存储器控制器被配置为管理与用户数据相关联的第一组和第二组用户数据和保证代码。 如果第一组和第二组用户数据相同，则相同的数据集被存储在第一物理页中，并且第一和第二保证码被存储在第二物理页中。
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公开(公告)号：US20140189203A1
公开(公告)日：2014-07-03
申请号：US13811008
申请日：2012-12-28
Applicant: Hitachi, Ltd.
Inventor： Akifumi Suzuki , Junji Ogawa , Akira Yamamoto
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F12/0866 , G06F12/0868 , G06F12/0871 , G06F2212/222 , G06F2212/282 , G06F2212/502
Abstract: A cache memory (CM) in which data, which is accessed with respect to a storage device, is temporarily stored is coupled to a controller for accessing the storage device in accordance with an access command from a higher-level apparatus. The CM comprises a nonvolatile semi-conductor memory (NVM), and provides a logical space to the controller. The controller is configured to partition the logical space into multiple segments and to manage these segments, and to access the CM by specifying a logical address of the logical space. The CM receives the logical address-specified access, and accesses a physical area allocated to a logical area, which belongs to the specified logical address. A first management unit, which is a unit of a segment, is larger than a second management unit, which is a unit of an access performed with respect to the NVM. The capacity of the logical space is larger than the storage capacity of the NVM.
Abstract translation: 临时存储关于存储装置访问的数据的高速缓存存储器（CM）被耦合到控制器，用于根据来自上级装置的访问命令访问存储装置。 CM包括非易失性半导体存储器（NVM），并向控制器提供逻辑空间。 控制器被配置为将逻辑空间划分成多个段并且管理这些段，并且通过指定逻辑空间的逻辑地址来访问CM。 CM接收逻辑地址指定的访问，并访问分配给属于指定逻辑地址的逻辑区域的物理区域。 作为段的单位的第一管理单元大于作为相对于NVM执行的访问的单位的第二管理单元。 逻辑空间的容量大于NVM的存储容量。
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公开(公告)号：US20220334726A1
公开(公告)日：2022-10-20
申请号：US17474562
申请日：2021-09-14
Applicant: Hitachi, Ltd.
Inventor： Shugo Ogawa , Akira Yamamoto , Yoshinori Ohira , Ryosuke Tatsumi , Junji Ogawa , Hiroto Ebara
IPC: G06F3/06
Abstract: One or a plurality of physical storage devices that provide a physical storage area are connected to first and second computers. The computer updates metadata indicating the address correspondence relationship between the logical address of the volume and the physical address of the physical storage area in the write processing performed based on a write request designating the volume. The first computer copies the metadata to the second computer while receiving the write request. When the address correspondence relationship indicated by the copied metadata portion is changed during copying of the metadata, the first computer updates the metadata portion and copies the metadata portion to the second computer.
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公开(公告)号：US10360144B2
公开(公告)日：2019-07-23
申请号：US15545094
申请日：2015-02-27
Applicant: HITACHI, LTD.
Inventor： Masatsugu Oshimi , Yoshihiro Oikawa , Hiroshi Hirayama , Junji Ogawa
Abstract: A storage apparatus includes a non-volatile memory and a controller to determine whether or not to compress data at a time when a non-volatile memory device receives the data from a host apparatus. A storage controller transmits a specified logical address range, an update frequency level of the specified logical address range, and specified data to a device controller. The update frequency level may indicate whether data is Hot or Cold. On the basis of the update frequency level of the specified logical address range, the device controller determines whether to compress the specified data. When a determination is made to compress the specified data, the device controller compresses the specified data to generate compressed data, and writes the compressed data into a non-volatile memory which may be a flash memory device. A degradation rank of physical blocks in the flash memory may include at least Young and Old. Reclamation processing including selecting a migration destination on the basis of the updated frequency level may also be performed. When a determination is made not to compress the specified data, the device controller writes the specified data into the non-volatile memory.
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公开(公告)号：US10310758B2
公开(公告)日：2019-06-04
申请号：US15122770
申请日：2014-03-26
Applicant: HITACHI, LTD.
Inventor： Miho Imazaki , Norio Simozono , Junji Ogawa , Tomohiro Yoshihara , Akira Yamamoto , Hiroaki Akutsu
Abstract: A second virtual volume having a plurality of second virtual areas is a clone of a first virtual volume having a plurality of first virtual areas. A first real area is allocated from a pool of real areas and based on storage devices to the first virtual volume. A storage controller allocates a second real area to the second virtual area before a write occurs in the second virtual area corresponding to the first virtual area to which the first real area is allocated. A physical area is allocated to a logical area corresponding to the first real area in each storage device, and data based on user data stored in the first real area is stored in the physical area. Each storage device allocates the physical area allocated to the logical area corresponding to the first real area to a logical area corresponding to the second real area.
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