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公开(公告)号：US20240273368A1
公开(公告)日：2024-08-15
申请号：US18636640
申请日：2024-04-16
Applicant: Google LLC
Inventor： Gregory Michael Thorson , Christopher Aaron Clark , Dan Luu
Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.
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公开(公告)号：US11620508B2
公开(公告)日：2023-04-04
申请号：US16245406
申请日：2019-01-11
Applicant: Google LLC
Inventor： Gregory Michael Thorson , Christopher Aaron Clark , Dan Luu
Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.
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公开(公告)号：US10956537B2
公开(公告)日：2021-03-23
申请号：US16840972
申请日：2020-04-06
Applicant: Google LLC
Inventor： Dong Hyuk Woo , Gregory Michael Thorson , Andrew Everett Phelps , Olivier Temam , Jonathan Ross , Christopher Aaron Clark
Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.
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公开(公告)号：US20200301996A1
公开(公告)日：2020-09-24
申请号：US16840972
申请日：2020-04-06
Applicant: Google LLC
Inventor： Dong Hyuk Woo , Gregory Michael Thorson , Andrew Everett Phelps , Olivier Temam , Jonathan Ross , Christopher Aaron Clark
Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.
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公开(公告)号：US10074051B2
公开(公告)日：2018-09-11
申请号：US15389288
申请日：2016-12-22
Applicant: Google LLC
Inventor： Gregory Michael Thorson , Christopher Aaron Clark , Dan Luu
Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.
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Patent Agency Ranking
公开(公告)号：US20180253403A1
公开(公告)日：2018-09-06
申请号：US15966275
申请日：2018-04-30
Applicant: Google LLC
Inventor： Dong Hyuk Woo , Gregory Michael Thorson , Andrew Everett Phelps , Olivier Temam , Jonathan Ross , Christopher Aaron Clark
IPC: G06F17/16
CPC classification number: G06F17/16 , G06F7/76 , G06F9/30032 , G06F9/30036
Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.
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公开(公告)号：US12277499B2
公开(公告)日：2025-04-15
申请号：US18636640
申请日：2024-04-16
Applicant: Google LLC
Inventor： Gregory Michael Thorson , Christopher Aaron Clark , Dan Luu
Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.
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公开(公告)号：US12182537B2
公开(公告)日：2024-12-31
申请号：US17175559
申请日：2021-02-12
Applicant: Google LLC
Inventor： Jonathan Ross , Robert David Nuckolls , Christopher Aaron Clark , Chester Li , Gregory Michael Thorson
Abstract: A circuit for transposing a matrix comprising reversal circuitry configured, for each of one or more diagonals of the matrix, to receive elements of the matrix in a first vector and generate a second vector that includes the elements of the matrix in an order that is a reverse of an order of the elements of the matrix in the first vector, and rotation circuitry configured, for each of the one or more diagonals of the matrix, to determine a number of positions by which to rotate the elements of the matrix in the second vector, receive the second vector of elements of the matrix, and generate a third vector that includes the elements of the matrix in the second vector in an order that is a rotation of the elements of the matrix in the second vector by the determined number of positions.
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公开(公告)号：US11520581B2
公开(公告)日：2022-12-06
申请号：US17327957
申请日：2021-05-24
Applicant: Google LLC
Inventor： William Lacy , Gregory Michael Thorson , Christopher Aaron Clark , Norman Paul Jouppi , Thomas Norrie , Andrew Everett Phelps
IPC: G06F9/30 , G06F15/80 , G06F9/38 , G06F7/58 , G06F13/36 , G06F13/40 , G06F13/42 , G06F17/16 , G06N3/063 , G06N20/00
Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.
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公开(公告)号：US20210357212A1
公开(公告)日：2021-11-18
申请号：US17327957
申请日：2021-05-24
Applicant: Google LLC
Inventor： William Lacy , Gregory Michael Thorson , Christopher Aaron Clark , Norman Paul Jouppi , Thomas Norrie , Andrew Everett Phelps
Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.
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