Two Stage Command Buffers To Overlap Iommu Map And Second Tier Memory Reads

    公开(公告)号:US20190227729A1

    公开(公告)日:2019-07-25

    申请号:US16373207

    申请日:2019-04-02

    申请人: Google LLC

    摘要: IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.

    Memory management supporting huge pages

    公开(公告)号:US10108550B2

    公开(公告)日:2018-10-23

    申请号:US15273433

    申请日:2016-09-22

    申请人: Google LLC

    摘要: Methods, systems, and apparatus for receiving a request to access, from a main memory, data contained in a first portion of a first page of data, the first page of data having a first page size; initiating a page fault based on determining that the first page of data is not stored in the main memory; allocating a portion of the main memory equivalent to the first page size; transferring the first portion of the first page of data from the secondary memory to the allocated portion of the main memory without transferring the entire first page of data; and updating a first page table entry associated with the first portion of the first page of data to point to a location of the allocated portion of the main memory to which the first portion of the first page of data is transferred.

    Hybrid memory management
    5.
    发明授权

    公开(公告)号:US10705975B2

    公开(公告)日:2020-07-07

    申请号:US16182695

    申请日:2018-11-07

    申请人: Google LLC

    摘要: Methods, systems, and apparatus for determining whether an access bit is set for each page table entry of a page table based on a scan of the page table with at least one page table walker, the access bit indicating whether a page associated with the page table entry was accessed in a last scan period; incrementing a count for each page in response to determining that the access bit is set for the page table entry associated with the page; resetting the access bit after determining whether the access bit is set for each page table entry; receiving a request to access, from a main memory, a first page of data; initiating a page fault based on determining that the first page of data is not stored in the main memory; and servicing the page fault with a DMA engine.

    Hybrid memory management
    6.
    发明授权

    公开(公告)号:US10152427B2

    公开(公告)日:2018-12-11

    申请号:US15235495

    申请日:2016-08-12

    申请人: Google LLC

    摘要: Methods, systems, and apparatus for determining whether an access bit is set for each page table entry of a page table based on a scan of the page table with at least one page table walker, the access bit indicating whether a page associated with the page table entry was accessed in a last scan period; incrementing a count for each page in response to determining that the access bit is set for the page table entry associated with the page; resetting the access bit after determining whether the access bit is set for each page table entry; receiving a request to access, from a main memory, a first page of data; initiating a page fault based on determining that the first page of data is not stored in the main memory; and servicing the page fault with a DMA engine.

    HYBRID MEMORY MANAGEMENT
    7.
    发明申请

    公开(公告)号:US20190073314A1

    公开(公告)日:2019-03-07

    申请号:US16182695

    申请日:2018-11-07

    申请人: Google LLC

    IPC分类号: G06F12/1009 G06F12/121

    摘要: Methods, systems, and apparatus for determining whether an access bit is set for each page table entry of a page table based on a scan of the page table with at least one page table walker, the access bit indicating whether a page associated with the page table entry was accessed in a last scan period; incrementing a count for each page in response to determining that the access bit is set for the page table entry associated with the page; resetting the access bit after determining whether the access bit is set for each page table entry; receiving a request to access, from a main memory, a first page of data; initiating a page fault based on determining that the first page of data is not stored in the main memory; and servicing the page fault with a DMA engine.