公开(公告)号：US10032695B2

公开(公告)日：2018-07-24

申请号：US15048140

申请日：2016-02-19

Applicant: Google Inc.

Inventor： Madhu Krishnan Iyengar ,  Teck-Gyu Kang ,  Christopher Gregory Malone ,  Norman Paul Jouppi

IPC: H01L23/473 ,  H01L23/04 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L25/18 ,  H01L23/44 ,  H01L25/065

Abstract: A semiconductor package includes a substrate, an integrated circuit disposed on the substrate, a memory support disposed on the integrated circuit, stacked memory disposed on the memory support and in communication with the integrated circuit, and a lid connected to the substrate. The integrated circuit has a low power region and a high power region. The memory support is disposed on the low power region of the integrated circuit and is configured to allow a flow of fluid therethrough to conduct heat away from the low power region of the integrated circuit. The lid defines a first port, a second port, and a lid volume fluidly connecting the first port and the second port. The lid volume is configured to house the integrated circuit, the memory support, and the stacked memory, while directing the flow of fluid to flow over the integrated circuit, the memory support, and the stacked memory.

公开(公告)号：US09747546B2

公开(公告)日：2017-08-29

申请号：US14844524

申请日：2015-09-03

Applicant: Google Inc.

Inventor： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC: G06N3/06 ,  G06N3/063 ,  G06F15/80

CPC classification number: G06N3/08 ,  G06F15/8046 ,  G06N3/063 ,  G06N5/04

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

公开(公告)号：US20170243806A1

公开(公告)日：2017-08-24

申请号：US15048140

申请日：2016-02-19

Applicant: Google Inc.

Inventor： Madhu Krishnan Iyengar ,  Teck-Gyu Kang ,  Christopher Gregory Malone ,  Norman Paul Jouppi

IPC: H01L23/473 ,  H01L25/18 ,  H01L23/373 ,  H01L23/498 ,  H01L23/04 ,  H01L23/367

CPC classification number: H01L23/473 ,  H01L23/04 ,  H01L23/3675 ,  H01L23/3732 ,  H01L23/3736 ,  H01L23/3737 ,  H01L23/44 ,  H01L23/498 ,  H01L25/0652 ,  H01L25/18

Abstract: A semiconductor package includes a substrate, an integrated circuit disposed on the substrate, a memory support disposed on the integrated circuit, stacked memory disposed on the memory support and in communication with the integrated circuit, and a lid connected to the substrate. The integrated circuit has a low power region and a high power region. The memory support is disposed on the low power region of the integrated circuit and is configured to allow a flow of fluid therethrough to conduct heat away from the low power region of the integrated circuit. The lid defines a first port, a second port, and a lid volume fluidly connecting the first port and the second port. The lid volume is configured to house the integrated circuit, the memory support, and the stacked memory, while directing the flow of fluid to flow over the integrated circuit, the memory support, and the stacked memory.

公开(公告)号：US20180260220A1

公开(公告)日：2018-09-13

申请号：US15454214

申请日：2017-03-09

Applicant: Google Inc.

Inventor： William Lacy ,  Gregory Michael Thorson ,  Christopher Aaron Clark ,  Norman Paul Jouppi ,  Thomas Norrie ,  Andrew Everett Phelps

IPC: G06F9/30 ,  G06F13/40 ,  G06F13/36 ,  G06F13/42 ,  G06F15/80 ,  G06F17/16 ,  G06F7/58

CPC classification number: G06F9/3001 ,  G06F7/588 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F13/36 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/8046 ,  G06F15/8053 ,  G06F15/8092 ,  G06F17/16 ,  G06N3/063

Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.

公开(公告)号：US20180046907A1

公开(公告)日：2018-02-15

申请号：US15686615

申请日：2017-08-25

Applicant: Google Inc.

Inventor： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC: G06N3/063 ,  G06F15/80

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

公开(公告)号：US09710748B2

公开(公告)日：2017-07-18

申请号：US15389202

申请日：2016-12-22

Applicant: Google Inc.

Inventor： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC: G06N3/08 ,  G06N5/04

CPC classification number: G06N3/08 ,  G06F15/8046 ,  G06N3/063 ,  G06N5/04

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

公开(公告)号：US20170103313A1

公开(公告)日：2017-04-13

申请号：US15389202

申请日：2016-12-22

Applicant: Google Inc.

Inventor： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC: G06N3/08 ,  G06N5/04

CPC classification number: G06N3/08 ,  G06F15/8046 ,  G06N3/063 ,  G06N5/04

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

公开(公告)号：US20160342891A1

公开(公告)日：2016-11-24

申请号：US14844524

申请日：2015-09-03

Applicant: Google Inc.

Inventor： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC: G06N3/08 ,  G06N99/00

CPC classification number: G06N3/08 ,  G06F15/8046 ,  G06N3/063 ,  G06N5/04

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

Abstract translation: 一种用于对包括多个神经网络层的神经网络执行神经网络计算的电路，所述电路包括：矩阵计算单元，被配置为针对所述多个神经网络层中的每个神经网络层：接收多个权重输入和多个 用于所述神经网络层的激活输入，并且基于所述多个权重输入和所述多个激活输入生成多个累积值; 以及矢量计算单元，其通信地耦合到所述矩阵计算单元，并且被配置为针对所述多个神经网络层中的每个神经网络层：将激活函数应用于由所述矩阵计算单元生成的每个累积值，以生成所述神经元的多个激活值 网络层。