公开(公告)号：US20150011056A1

公开(公告)日：2015-01-08

申请号：US14323177

申请日：2014-07-03

Applicant: Gold Standard Simulations Ltd.

Inventor： Ashok K. Kapoor ,  Asen Asenov

IPC: H01L29/66

CPC classification number: H01L29/66537 ,  H01L21/28088 ,  H01L29/1083 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7848 ,  H01L29/78654 ,  H01L29/78669 ,  H01L29/78684

Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a recess in the underlying is formed using a crystallographic etch to provide [111] boundaries adjacent the source and drain regions. An ion implant step localized by the cavity results in a localized increase in well-doping directly beneath the recess. Within the recess, an active region is formed using an un-doped or lightly doped epitaxial layer, deposited at a very low temperature. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries.

Abstract translation: 使用高K金属栅极“通道最后”工艺制造耐变压金属氧化物半导体场效应晶体管（MOSFET）。 在形成在具有单独的漏极和源极区域的阱区域之间的间隔物之间​​，使用晶体学蚀刻形成下面的凹陷，以提供邻近源极和漏极区域的[111]边界。 通过腔定位的离子注入步骤导致在凹陷下方的阱掺杂的局部增加。 在凹槽内，使用在非常低的温度下沉积的未掺杂或轻掺杂的外延层形成有源区。 在轻掺杂的外延层上形成高K电介质堆叠，在腔边界内形成金属栅极。

公开(公告)号：US09012276B2

公开(公告)日：2015-04-21

申请号：US14323177

申请日：2014-07-03

Applicant: Gold Standard Simulations Ltd.

Inventor： Ashok K. Kapoor ,  Asen Asenov

IPC: H01L21/00 ,  H01L29/66

CPC classification number: H01L29/66537 ,  H01L21/28088 ,  H01L29/1083 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7848 ,  H01L29/78654 ,  H01L29/78669 ,  H01L29/78684

Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a recess in the underlying is formed using a crystallographic etch to provide [111] boundaries adjacent the source and drain regions. An ion implant step localized by the cavity results in a localized increase in well-doping directly beneath the recess. Within the recess, an active region is formed using an un-doped or lightly doped epitaxial layer, deposited at a very low temperature. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries.

Abstract translation: 使用高K金属栅极“通道最后”工艺制造耐变压金属氧化物半导体场效应晶体管（MOSFET）。 在形成在具有单独的漏极和源极区域的阱区域之间的间隔物之间​​，使用晶体学蚀刻形成下面的凹陷，以提供邻近源极和漏极区域的[111]边界。 通过腔定位的离子注入步骤导致在凹陷下方的阱掺杂的局部增加。 在凹槽内，使用在非常低的温度下沉积的未掺杂或轻掺杂的外延层形成有源区。 在轻掺杂的外延层上形成高K电介质堆叠，在腔边界内形成金属栅极。

公开(公告)号：US20140103437A1

公开(公告)日：2014-04-17

申请号：US14051163

申请日：2013-10-10

Applicant: Gold Standard Simulations Ltd. ,  Semi Solutions LLC

Inventor： Ashok K. Kapoor ,  Robert J. Strain

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7853

Abstract: An improved fin field-effect transistor (FinFET) is built on a compound fin, which has a doped core and lightly doped epitaxial channel region between that core and the gate dielectric. The improved structure reduces FinFET random doping fluctuations when doping is used to control threshold voltage. Further, the transistor design affords better source and drain conductance when compared to prior art FinFETs. Three representative embodiments of the key structure are described in detail.

Abstract translation: 改进的鳍状场效应晶体管（FinFET）构建在复合鳍片上，复合鳍片在该芯体和栅极电介质之间具有掺杂的核心和轻掺杂的外延沟道区域。 当掺杂用于控制阈值电压时，改进的结构减少了FinFET随机掺杂波动。 此外，与现有技术的FinFET相比，晶体管设计提供更好的源极和漏极电导。 详细描述键结构的三个代表性实施例。