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    ELECTRIC, WATER VAPOR DIFFUSION RESISTANT PIN-AND-SOCKET CONNECTOR
    1.
    发明申请
    ELECTRIC, WATER VAPOR DIFFUSION RESISTANT PIN-AND-SOCKET CONNECTOR 审中-公开
    电动，水蒸气扩散插头和插座连接器

    公开(公告)号：US20110212640A1

    公开(公告)日：2011-09-01

    申请号：US12995454

    申请日：2009-05-28

    Applicant: Gerrit Lange ,  Karl-Friedrich Haarburger

    Inventor： Gerrit Lange ,  Karl-Friedrich Haarburger

    IPC: H01R13/52

    CPC classification number: H01R13/5202 ,  H01L31/02008 ,  H01R13/746 ,  Y02E10/50

    Abstract: A nonconductive plate that is plated-through with an electric pin-and-socket connector in a water vapor diffusion resistant manner as well as its use as back side or side wall of a photovoltaic module is provided. The electric pin-and-socket connector includes a push-through element and a pressing element as well as a sealing element located on the pressing element and made of a material with a low water vapor diffusion rate. By the engagement of the push-through element into a retention element on a second side of the nonconducting plate, the sealing element is pressed against the first side of the plate by the pressing element and thus seals the bore in the plate in a water vapor diffusion resistant manner.

    Abstract translation: 提供了一种具有电插销连接器的电镀通孔的非导电板，其具有防水蒸气扩散的方式以及其作为光伏模块的背侧或侧壁的用途。 电插销连接器包括推进元件和按压元件以及位于按压元件上并由具有低水蒸气扩散速率的材料制成的密封元件。 通过将推通元件接合到不导电板的第二侧上的保持元件中，密封元件通过按压元件压靠在板的第一侧上，从而以水蒸气密封板中的孔 扩散阻力。

    Manufacturing method for a capacitor in an integrated memory circuit
    2.
    发明授权
    Manufacturing method for a capacitor in an integrated memory circuit 有权
    集成存储电路中电容器的制造方法

    公开(公告)号：US06204119B1

    公开(公告)日：2001-03-20

    申请号：US09312572

    申请日：1999-05-14

    Applicant: Gerrit Lange ,  Martin Franosch ,  Wolfgang Hönlein ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schäfer ,  Reinhard Stengl ,  Hermann Wendt

    Inventor： Gerrit Lange ,  Martin Franosch ,  Wolfgang Hönlein ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schäfer ,  Reinhard Stengl ,  Hermann Wendt

    IPC: H01L218242

    CPC classification number: H01L28/87 ,  Y10S438/97

    Abstract: A manufacturing method for a capacitor in an integrated memory circuit includes initially depositing a first conducting layer and an auxiliary layer acting as an etch-stop onto a carrier. Then a layer sequence which contains alternating layers of the first material and a second material is produced on top of the first conducting layer and the auxiliary layer. The layer sequence may, in particular, have p+/p− silicon layers or silicon/germanium layers. A layer structure with a base of a capacitor to be produced is formed from the layer sequence. Sides of the layer structure are provided with a conducting supporting structure. An opening is formed inside the layer structure, all the way down to the auxiliary layer and then the auxiliary layer and the layers made of the second material are removed. A free surface of the layers made of the first material and the supporting structure are provided with a capacitor dielectric onto which a counter electrode is applied.

    Abstract translation: 集成存储器电路中的电容器的制造方法包括：首先将作为蚀刻停止层的第一导电层和辅助层沉积到载体上。 然后在第一导电层和辅助层的顶部上产生包含第一材料和第二材料的交替层的层序列。 层序列可以具体地具有p + / p-硅层或硅/锗层。 从层序列形成具有要制造的电容器的基极的层结构。 层结构的侧面设置有导电支撑结构。 在层结构内形成一个开口，一直到辅助层，然后除去辅助层和由第二材料制成的层。 由第一材料和支撑结构制成的层的自由表面设置有施加对电极的电容器电介质。

    Manufacturing method for a capacitor in an integrated storage circuit
    3.
    发明授权
    Manufacturing method for a capacitor in an integrated storage circuit 有权
    集成存储电路中电容器的制造方法

    公开(公告)号：US6127220A

    公开(公告)日：2000-10-03

    申请号：US312571

    申请日：1999-05-14

    Applicant: Gerrit Lange ,  Martin Franosch ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schafer ,  Reinhard Stengl ,  Hermann Wendt

    Inventor： Gerrit Lange ,  Martin Franosch ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schafer ,  Reinhard Stengl ,  Hermann Wendt

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10852 ,  H01L27/10817

    Abstract: On a carrier a layer sequence is applied which contains alternatingly layers made of a first conducting material and a second material in which both materials are different from a carrier material. An opening is made in the layer sequence, which is filled with a conducting material so that a central supporting structure is produced. Then the layer sequence is structured corresponding to the dimensions of a capacitor and the layers made of the second material are removed selectively, so that a first capacitor electrode is formed. The layer sequence may have especially p.sup.+ -/p.sup.- silicon layers or silicon/germanium layers. An etch-stop layer can also be incorporated as the lowest or second-lowest layer.

    Abstract translation: 在载体上施加层序列，其包含由第一导电材料和第二材料制成的交替层，其中两种材料都不同于载体材料。 在层序列中形成开口，其中填充有导电材料，从而产生中心支撑结构。 然后根据电容器的尺寸构造层序列，并且选择性地去除由第二材料制成的层，从而形成第一电容器电极。 层序列可以具有特别的p + - / p-硅层或硅/锗层。 也可以将蚀刻停止层作为最低层或第二层加入。

    Capacitor with high-&egr; dielectric or ferroelectric material based on the fin stack principle
    5.
    发明授权
    Capacitor with high-&egr; dielectric or ferroelectric material based on the fin stack principle 有权
    基于鳍片堆叠原理的具有高ε电介质或铁电材料的电容器

    公开(公告)号：US06512259B1

    公开(公告)日：2003-01-28

    申请号：US09863925

    申请日：2001-05-23

    Applicant: Gerrit Lange ,  Till Schlösser

    Inventor： Gerrit Lange ,  Till Schlösser

    IPC: H01L27108

    CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/88

    Abstract: A capacitor in a semiconductor configuration on a substrate includes a noble-metal-containing first capacitor electrode which is formed with a plurality of mutually spaced-apart lamellae. The lamellae are oriented substantially parallel to a surface of the substrate and are mechanically and electrically connected to one another on a flank by a support structure. The capacitor furthermore has a capacitor dielectric formed of high-∈ dielectric or ferroelectric material disposed on the first capacitor electrode. The capacitor also has a second capacitor electrode on the capacitor dielectric.

    Abstract translation: 在基板上的半导体结构中的电容器包括形成有多个相互间隔开的薄片的含贵金属的第一电容器电极。 薄片基本上平行于基底的表面定向，并且在侧面通过支撑结构彼此机械地和电连接。 电容器还具有由设置在第一电容器电极上的电介质或铁电材料中的高电介质形成的电容器电介质。 电容器还在电容器电介质上具有第二电容器电极。

    Electrically programmable non-volatile memory cell configuration
    8.
    发明授权
    Electrically programmable non-volatile memory cell configuration 有权
    电可编程非易失性存储单元配置

    公开(公告)号：US06215140B1

    公开(公告)日：2001-04-10

    申请号：US09398691

    申请日：1999-09-20

    Applicant: Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    Inventor： Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    IPC: H01L2972

    CPC classification number: H01L21/8229 ,  H01L27/1021

    Abstract: A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls of the trenches. Second address lines are formed on the semiconductor substrate, transversely with respect to the trenches. Semiconductor substrate regions, in which a diode and a dielectric whose conductivity can be changed are arranged, are located between the first address lines and the second address lines. A suitable current pulse can be used to produce a breakdown in the dielectric, with information thus being stored in the dielectric.

    Abstract translation: 提出半导体衬底中的存储单元结构，其中半导体衬底是第一导电类型。 相互平行延伸的沟槽并入半导体衬底中，并且第一地址线沿着沟槽的侧壁延伸。 第二地址线在半导体衬底上相对于沟槽横向地形成。 布置有可以改变导电性的二极管和电介质的半导体衬底区域位于第一地址线和第二地址线之间。 可以使用合适的电流脉冲来产生电介质中的击穿，由此将信息存储在电介质中。

    Method for fabricating a dopant region
    9.
    发明授权
    Method for fabricating a dopant region 有权
    掺杂剂区域的制造方法

    公开(公告)号：US6133126A

    公开(公告)日：2000-10-17

    申请号：US398688

    申请日：1999-09-20

    Applicant: Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    Inventor： Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    IPC: H01L21/225 ,  H01L21/768 ,  H01L21/8239 ,  H01L27/105 ,  H01L21/22

    CPC classification number: H01L21/76888 ,  H01L21/2256 ,  H01L27/105 ,  H01L27/1052

    Abstract: A method for fabricating a dopant region is disclosed. The dopant region is formed by providing a semiconductor substrate that has a surface. An electrically insulating intermediate layer is applied to the surface. A doped semiconductor layer is then applied to the electrically insulating intermediate layer, the semiconductor layer being of a first conductivity type and contains a dopant of the first conductivity type. A temperature treatment of the semiconductor substrate at a predefined diffusion temperature is performed, so that the dopant diffuses partially out of the semiconductor layer through the intermediate layer into the semiconductor substrate and forms there a dopant region of the first conductivity type. The electrical conductivity of the intermediate layer is modified, so that an electrical contact between the semiconductor substrate and the semiconductor layer is produced through the intermediate layer.

    Abstract translation: 公开了一种制造掺杂剂区域的方法。 通过提供具有表面的半导体衬底形成掺杂剂区域。 将电绝缘的中间层施加到表面。 然后将掺杂半导体层施加到电绝缘中间层，所述半导体层是第一导电类型并且包含第一导电类型的掺杂剂。 执行预定扩散温度下的半导体衬底的温度处理，使得掺杂剂从半导体层中部分扩散通过中间层进入半导体衬底，并在其上形成第一导电类型的掺杂区域。 改变中间层的导电性，从而通过中间层产生半导体衬底和半导体层之间的电接触。

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