公开(公告)号：US07368752B2

公开(公告)日：2008-05-06

申请号：US10839800

申请日：2004-05-06

申请人： Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

发明人： Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

IPC分类号： H01L27/108 ,  H01L29/12 ,  H01L31/112

CPC分类号： H01L27/10823 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10891 ,  H01L29/7851

摘要： A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.

摘要翻译： DRAM存储单元设置有选择晶体管，该晶体管被水平地布置在半导体衬底表面处并且具有第一源极/漏极，第二源极/漏极，布置在第一和第二源极/漏极之间的沟道层 在所述半导体基板中，沿着所述沟道层配置并与所述沟道层电绝缘的栅电极具有与所述第一电容电极绝缘的第一电容电极和第二电容电极的保持电容器， 所述存储电容器的电容器电极与所述选择晶体管的源极/漏极之一导电地连接，并且在后侧具有半导体衬底电极，所述栅电极在至少两个相对的两侧包围所述沟道层。

公开(公告)号：US06822916B2

公开(公告)日：2004-11-23

申请号：US09796207

申请日：2001-06-01

申请人： Alexander Frey ,  Werner Weber ,  Till Schlösser

发明人： Alexander Frey ,  Werner Weber ,  Till Schlösser

IPC分类号： G11C700

CPC分类号： H01L27/10894 ,  G11C11/4091 ,  H01L27/10876 ,  H01L27/10897

摘要： As a consequence of DRAM memory cell miniaturization, the available space for read/write amplifiers decreases in width from hitherto 4 bit line grids to 2 bit lines grids. Conventionally previously known read/write amplifiers cannot be accommodated on this reduced, still available space. Therefore, it has not been possible hitherto to provide read/write amplifiers arranged beside one another which would manage with the novel DRAM memory cell spacings. The principle underlying the invention is based on replacing at least some of the transistors of conventional design which are usually used for read/write circuits by “vertical transistors” in which the differently doped regions are arranged one above the other or practically one above the other. Compared with the use of conventional transistors, the use of vertical transistors saves enough space to ensure an arrangement of a read/write circuit in the grid even with a reduced grid width.

摘要翻译： 作为DRAM存储单元小型化的结果，用于读/写放大器的可用空间从迄今为止的4位线栅格宽度减小到2位线栅格。 常规的已知的读/写放大器不能适应这个缩小的仍然可用的空间。 因此，到目前为止还不可能提供一个旁边配置的读/写放大器，这些放大器将利用新颖的DRAM存储器单元间隔进行管理。 本发明的原理是基于将通常用于读/写电路的常规设计的至少一些晶体管替换为“垂直晶体管”，其中不同掺杂区域一个在另一个上方布置或实际上一个在另一个之上 。 与使用常规晶体管相比，垂直晶体管的使用节省了足够的空间，以确保即使在减小的栅格宽度的情况下也能在网格中布置读/写电路。

公开(公告)号：US06750098B2

公开(公告)日：2004-06-15

申请号：US10619970

申请日：2003-07-15

申请人： Till Schlösser ,  Dirk Manger

发明人： Till Schlösser ,  Dirk Manger

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/66666

摘要： In semiconductor memories having a surrounding gate configuration, webs, i.e. vertical rectangular pillars made of substrate material, are formed at the surface of a semiconductor substrate and are surrounded by the gate electrodes in a lower region. Conventionally, it is not possible for word lines to make contact with the gate electrodes in the lower region of the webs without at the same time electrically influencing substrate regions at a higher level in the webs or short-circuiting bit lines from their sidewalls, unless complicated methods requiring additional lithography steps are used. A method for the self-aligning, selective contact-connection of the peripheral gate electrodes is performed with the aid of an insulation layer having a smaller layer thickness than the peripheral gate electrodes.

摘要翻译： 在具有围绕栅极结构的半导体存储器中，在半导体衬底的表面上形成由衬底材料制成的腹板，即垂直矩形柱，并且在下部区域中由栅电极包围。 通常，字线不可能与幅材的下部区域中的栅极电极接触，而不会同时在幅材或短路位线从其侧壁电位影响衬底区域的较高水平，除非 使用需要额外光刻步骤的复杂方法。 借助于具有比外围栅极电极更薄的层厚度的绝缘层来执行外围栅电极的自对准，选择性接触连接的方法。

公开(公告)号：US06512259B1

公开(公告)日：2003-01-28

申请号：US09863925

申请日：2001-05-23

申请人： Gerrit Lange ,  Till Schlösser

发明人： Gerrit Lange ,  Till Schlösser

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/88

摘要： A capacitor in a semiconductor configuration on a substrate includes a noble-metal-containing first capacitor electrode which is formed with a plurality of mutually spaced-apart lamellae. The lamellae are oriented substantially parallel to a surface of the substrate and are mechanically and electrically connected to one another on a flank by a support structure. The capacitor furthermore has a capacitor dielectric formed of high-∈ dielectric or ferroelectric material disposed on the first capacitor electrode. The capacitor also has a second capacitor electrode on the capacitor dielectric.

摘要翻译： 在基板上的半导体结构中的电容器包括形成有多个相互间隔开的薄片的含贵金属的第一电容器电极。 薄片基本上平行于基底的表面定向，并且在侧面通过支撑结构彼此机械地和电连接。 电容器还具有由设置在第一电容器电极上的电介质或铁电材料中的高电介质形成的电容器电介质。 电容器还在电容器电介质上具有第二电容器电极。

公开(公告)号：US06445609B2

公开(公告)日：2002-09-03

申请号：US09801715

申请日：2001-03-09

申请人： Alexander Frey ,  Werner Weber ,  Till Schlösser

发明人： Alexander Frey ,  Werner Weber ,  Till Schlösser

IPC分类号： G11C1194

CPC分类号： H01L27/10882 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10885 ,  H01L27/10897

摘要： A DRAM memory (50) having a number of DRAM memory cells (51) is described, the memory cells (51) in each case having a storage capacitor (52) and a selection transistor (12) which are formed in the area of an at least essentially rectangular cell area (59), the cell areas (59) having a greater extent in the longitudinal direction (L) than in the width direction (B) and which are wired or can be wired to the cell periphery via a word line (56, 57) and a bit line (55). The word lines (56, 57) and the bit line (55) are conducted over the memory cells (51) and are at least essentially oriented perpendicularly to one another. To achieve, with increasing miniaturization of the DRAM memory patterns, during the transition from so-called “folded” bit line architectures to so-called “open” bit line architectures that the bit line grid, and thus also the grid of corresponding read/write amplifiers, varies linearly in scale with the longitudinal extent (L) of the memory cells (51), it is provided according to the invention that the bit lines (55) are now oriented perpendicularly to the longitudinal extent (L) of the memory cells (51) in the direction of the lateral extent (B) of the memory cells (51)

摘要翻译： 描述了具有多个DRAM存储单元（51）的DRAM存储器（50），每个情况下的存储单元（51）具有存储电容器（52）和选择晶体管（12） 至少基本上矩形的单元区域（59），所述单元区域（59）在纵向方向（L）上比在宽度方向（B）上具有更大的程度，并且它们被布线或可以经由字连接到单元周边 线（56,57）和位线（55）。 字线（56,57）和位线（55）在存储器单元（51）上传导，并且至少基本上彼此垂直定向。 为了实现随着DRAM存储器模式的小型化，在从所谓的“折叠”位线结构转变到所谓的“开放”位线架构，即位线格栅，从而也是对应读/ 写放大器随着存储器单元（51）的纵向延伸（L）而在尺度上线性变化，根据本发明，提供了位线（55）垂直于存储器的纵向延伸（L）定向 在存储单元（51）的横向范围（B）的方向上的单元（51）

公开(公告)号：US07329916B2

公开(公告)日：2008-02-12

申请号：US11158439

申请日：2005-06-22

申请人： Till Schlösser ,  Brian S. Lee

发明人： Till Schlösser ,  Brian S. Lee

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10858 ,  H01L27/10852 ,  H01L27/10876

摘要： The invention is related to a DRAM cell arrangement with vertical MOS transistors. Channel regions arranged along one of the columns of a memory cell matrix are parts of a rib which is surrounded by a gate dielectric layer. Gate electrodes of the MOS transistors belonging to one row are parts of a strip-like word line, so that at each crossing point of the memory cell matrix there is a vertical dual-gate MOS transistor with gate electrodes of the associated word line formed in the trenches on both sides of the associated rib.

摘要翻译： 本发明涉及具有垂直MOS晶体管的DRAM单元布置。 沿着存储单元矩阵的一列排列的通道区域是由栅介质层包围的肋的部分。 属于一行的MOS晶体管的栅电极是条状字线的一部分，因此在存储单元矩阵的每个交叉点存在垂直双栅极MOS晶体管，其中形成相关联的字线的栅电极 相关肋骨两侧的沟槽。

公开(公告)号：US06916721B2

公开(公告)日：2005-07-12

申请号：US10722360

申请日：2003-11-26

申请人： Lars Heineck ,  Stephan Kudelka ,  Jörn Lützen ,  Hans-Peter Moll ,  Martin Popp ,  Till Schlösser ,  Johann Steinmetz

发明人： Lars Heineck ,  Stephan Kudelka ,  Jörn Lützen ,  Hans-Peter Moll ,  Martin Popp ,  Till Schlösser ,  Johann Steinmetz

IPC分类号： H01L21/20 ,  H01L21/334 ,  H01L21/425 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10867 ,  H01L27/10829 ,  H01L29/66181 ,  H01L29/945

摘要： A method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, using a hard mask with a corresponding mask opening.

摘要翻译： 一种在衬底中制造具有绝缘套环的沟槽电容器的方法，其使用具有相应掩模开口的硬掩模经由掩埋触点将其一侧的衬底电连接。

公开(公告)号：US06576948B2

公开(公告)日：2003-06-10

申请号：US09873231

申请日：2001-06-04

申请人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser ,  Josef Willer

发明人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser ,  Josef Willer

IPC分类号： H01L27108

CPC分类号： H01L27/108

摘要： An integrated circuit contains a planar first transistor and a diode. The diode is connected between a first source/drain region of the first transistor and a gate electrode of the first transistor such that a charge is impeded from discharging from the gate electrode to the first source/drain region. A diode layer that is part of the diode is disposed on a portion of the first source/drain region. A conductive structure that is an additional part of the diode is disposed above a portion of the gate electrode and is disposed on the diode layer. The diode can be configured as a tunnel diode. The diode layer can be produced by thermal oxidation. Only one mask is required for producing the diode. A capacitor can be disposed above the diode. The first capacitor electrode of the capacitor is connected to the conductive structure.

摘要翻译： 集成电路包含平面第一晶体管和二极管。 二极管连接在第一晶体管的第一源极/漏极区域和第一晶体管的栅电极之间，使得电荷被阻止从栅电极放电到第一源极/漏极区域。 作为二极管的一部分的二极管层设置在第一源极/漏极区域的一部分上。 作为二极管的附加部分的导电结构设置在栅电极的一部分上方并且设置在二极管层上。 二极管可以配置为隧道二极管。 二极管层可以通过热氧化生产。 制造二极管只需要一个掩模。 电容器可以设置在二极管的上方。 电容器的第一电容器电极连接到导电结构。

公开(公告)号：US06566193B2

公开(公告)日：2003-05-20

申请号：US10096473

申请日：2002-03-12

申请人： Franz Hofmann ,  Till Schlösser

发明人： Franz Hofmann ,  Till Schlösser

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10876

摘要： The process first forms trench capacitors in a substrate, which are filled with a trench fill and in which a first insulating layer is disposed over the conductive trench fill. The first insulating layer is then overgrown laterally by a selectively grown epitaxial layer. The selective epitaxial layer is so structured that a ridge is formed from it. Next, the ridge is partially undercut, whereby the etch selectivity of the ridge relative to the first insulating layer is utilized for a wet-chemical etching procedure. Next, a contact layer is arranged in the undercut region, which connects the ridge and a transistor that has been formed in the ridge to the conductive trench fill. Lateral margin ridges are then formed next to the ridge as a gate, and a doped region is incorporated into the ridge as a source/drain zone of the transistor.

公开(公告)号：US06534820B2

公开(公告)日：2003-03-18

申请号：US09745565

申请日：2000-12-21

申请人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser

发明人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser

IPC分类号： H01L29788

CPC分类号： H01L27/10844 ,  H01L27/108 ,  H01L27/10876

摘要： An integrated dynamic memory cell having a small area of extent on a semiconductor substrate is described. The memory cell has a selection MOSFET with a gate connection area that is connected to a word line, a source connection doping area which is connected to a bit line, and a drain connection doping area. A memory MOSFET has a gate connection area which is connected via a thin dielectric layer to a connection doping region which connects a source connection doping area of the memory MOSFET to the drain connection doping area of the selection MOSFET. The memory MOSFET further has a drain connection doping area that is connected to a supply voltage. The selection and memory MOSFETs are disposed on opposite sidewalls of a trench, which is etched in the substrate, and the connection doping region forms a bottom of the trench.

摘要翻译： 描述在半导体衬底上具有小面积范围的集成动态存储单元。 存储单元具有选择MOSFET，其具有连接到字线的栅极连接区域，连接到位线的源极连接掺杂区域和漏极连接掺杂区域。 存储器MOSFET具有通过薄介电层连接到将存储器MOSFET的源极连接掺杂区域连接到选择MOSFET的漏极连接掺杂区域的连接掺杂区域的栅极连接区域。 存储器MOSFET还具有连接到电源电压的漏极连接掺杂区域。 选择和存储器MOSFET被布置在沟槽的相对的侧壁上，沟槽被蚀刻在衬底中，并且连接掺杂区域形成沟槽的底部。