公开(公告)号：US20230266784A1

公开(公告)日：2023-08-24

申请号：US18303466

申请日：2023-04-19

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masashi AKAHANE

IPC: G05F1/59

CPC classification number: G05F1/59

Abstract: An integrated circuit includes: a power supply line configured to receive a power supply voltage; a constant current source electrically coupled to the power supply line;
a reference voltage circuit electrically coupled to the constant current source; and a first resistor having two ends, one end thereof being electrically coupled to the constant current source, and the other end thereof being electrically coupled to the reference voltage circuit. The reference voltage circuit is a bandgap circuit including a plurality pf bipolar devices. The first resistor is configured to decrease a leakage current in the bipolar devices when a temperature thereof rises.

公开(公告)号：US20220085798A1

公开(公告)日：2022-03-17

申请号：US17535336

申请日：2021-11-24

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masashi AKAHANE

IPC: H03K3/3565 ,  H03K5/24 ,  H03K17/687 ,  G01R19/165

Abstract: A comparator circuit configured to output an output voltage at a first logic level, upon an input voltage exceeding a first threshold voltage, and output the output voltage at a second logic level, upon the input voltage dropping below a second threshold voltage lower than the first threshold voltage. The comparator circuit includes a converter circuit configured to convert the input voltage of the comparator circuit into a first voltage and a second voltage lower than the first voltage, and a logic circuit configured to output a voltage, as the output voltage of the comparator circuit, that is at the first logic level, upon the first voltage exceeding a third threshold voltage, and at the second logic level, upon the second voltage dropping below a fourth threshold voltage lower than the third threshold voltage.

公开(公告)号：US20210184679A1

公开(公告)日：2021-06-17

申请号：US17185735

申请日：2021-02-25

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masashi AKAHANE

IPC: H03K19/0185 ,  H03K19/20

Abstract: A drive circuit having a set-side level shift circuit and a reset-side level shift circuit each configured to shift a level of a set or reset signal, and output the level-shifted set or reset signal from a set-side or reset-side output node, a mask-signal generating circuit configured to output a mask signal in response to a change in a voltage at the set-side or reset-side output node, and a control circuit configured to output a drive signal to a power device. The mask signal is for a time period shorter than a time period during which the level-shifted set or reset signal is outputted. The drive signal remains at a same level while the control circuit is receiving the mask signal, and switches to a first level or a second level, for turning off or on the power device, in response to the control circuit receiving the level-shifted reset or set signal after receiving the mask signal.

公开(公告)号：US20200244432A1

公开(公告)日：2020-07-30

申请号：US16847279

申请日：2020-04-13

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masashi AKAHANE

IPC: H04L7/00 ,  H04B3/02 ,  H03K17/567 ,  H04Q9/00 ,  G06F1/10 ,  G06F1/04 ,  G06F13/40 ,  H04L25/49

Abstract: A data communication system, including master-side and slave-side data communication apparatuses configured to perform bidirectional communication with each other via a single-wire communication line. The master-side data communication apparatus includes first and second transistors performing switching according respectively to an input clock and write data, and a master-side data reproduction circuit reproducing read data transmitted from the slave-side. The slave-side data communication apparatus includes a clock reproduction circuit and a slave-side data reproduction circuit configured to respectively reproduce the input clock and the write data transmitted from the master-side, and a third transistor performing switching both according to the input clock reproduced by the clock reproduction circuit and according to the read data.

公开(公告)号：US20190288592A1

公开(公告)日：2019-09-19

申请号：US16429066

申请日：2019-06-03

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masashi AKAHANE

IPC: H02M1/088 ,  H02M3/158 ,  H03K17/687 ,  H03K19/0175

Abstract: A drive device includes: a gate driving unit that has gate driving circuits each driving gates of switching elements connected to each other in series; a negative-side power source that supplies a negative potential to the gate driving unit, where the negative potential steps down a reference potential that is a potential on a low side of the switching element; a negative-side capacitor for supplying a negative potential to the gate driving unit, where the negative potential steps down a reference potential that is a potential on a high side of the switching element; a timing detecting circuit that detects charging timing at which the negative-side capacitor is to be charged based on a potential state of the gate driving circuit on a high side; and a charging circuit that charges the negative-side capacitor by using the negative-side power source at the charging timing.

公开(公告)号：US20180167063A1

公开(公告)日：2018-06-14

申请号：US15891188

申请日：2018-02-07

Applicant: Fuji Electric Co., Ltd.

Inventor： Masashi AKAHANE

IPC: H03K17/10 ,  H02M1/088

CPC classification number: H03K17/102 ,  H02M1/08 ,  H02M1/088 ,  H02M7/538 ,  H03K2217/0081

Abstract: A semiconductor device includes: a bootstrap capacitor charged via a diode when a low-side switching device is ON, a resulting charge voltage being applied to a high-side driver circuit when the low-side switching device is OFF; a supplementary bootstrap capacitor charged when the low-side switching device is OFF; a Zener diode that regulates a charge voltage of the supplementary bootstrap capacitor; and a control circuit that applies the charge voltage of the supplementary bootstrap capacitor to the high-side driver circuit via a switch circuit when the charge voltage of the bootstrap capacitor decreases to less than a prescribed voltage while a high-side switching device is ON.

公开(公告)号：US20140103736A1

公开(公告)日：2014-04-17

申请号：US14023554

申请日：2013-09-11

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masashi AKAHANE

IPC: H01F38/14

CPC classification number: H01F38/14 ,  H01F19/04 ,  H01F2019/085 ,  H04L25/0266

Abstract: A signal transmission device of aspects of the invention can include a master circuit connected to the primary sides of first and second transformers and a slave circuit connected to the secondary sides of the first and second transformers. The master circuit sets one of first and second transmitting/receiving circuits for transmitting operation and the other for receiving operation according to a control signal, and detecting a leading edge and a falling edge of the control signal, transmits a pulse signal with the pulse interval changing after a predetermined period of time. The slave circuit detects the change of the pulse interval of the signal received through third and fourth transmitting/receiving circuits and according to the detection result, sets one of the third and fourth transmitting/receiving circuits for receiving operation and the other for transmitting operation.

Abstract translation: 本发明的方面的信号传输装置可以包括连接到第一和第二变压器的初级侧的主电路和连接到第一和第二变压器的次级侧的从电路。 主电路设置用于发送操作的第一和第二发送/接收电路中的一个，另一个用于根据控制信号进行接收操作，并且检测控制信号的前沿和下降沿，发送脉冲间隔的脉冲信号 在预定的时间段之后改变。 从电路检测通过第三发送/接收电路接收的信号的脉冲间隔的变化，并且根据检测结果，设置用于接收操作的第三和第四发送/接收电路中的一个，另一个发送操作。

公开(公告)号：US20130293247A1

公开(公告)日：2013-11-07

申请号：US13861488

申请日：2013-04-12

Applicant: Fuji Electric Co., Ltd.

Inventor： Masashi AKAHANE

IPC: H03K17/56

CPC classification number: H03K17/56 ,  G01R27/02 ,  H03K17/04123 ,  H03K17/145 ,  H03K17/162 ,  H03K2217/0063 ,  H03K2217/0072 ,  H03K2217/0081

Abstract: A level shift circuit in which no adverse effect is produced on a delay time, regardless of the resistance values of resistors. The level shift circuit includes an operation detection circuit that outputs a nseten signal and a nresen signal in response to a state of output from first and second series circuits, a latch malfunction protection circuit connected to the operation detection circuit, a latch circuit connected through first to sixth resistors to first and second level shift output terminals of the first and second series circuits, first and second parasitic resistors, and third and fourth switching elements connected in parallel therewith, and fifth and sixth switching elements connected to a power source potential, a connection point of the first and second resistors or a connection point of the third and fourth resistors, and the operation detection circuit.

Abstract translation: 不考虑电阻器的电阻值的电平移位电路，其在延迟时间上不产生不利影响。 电平移位电路包括响应于来自第一和第二串联电路的输出状态而输出nseten信号和nresen信号的操作检测电路，连接到操作检测电路的闩锁故障保护电路，通过第一连接的锁存电路 到第一和第二串联电路的第一和第二电平移位输出端的第六电阻器，第一和第二寄生电阻器以及并联连接的第三和第四开关元件，以及连接到电源电位的第五和第六开关元件， 第一和第二电阻器的连接点或第三和第四电阻器的连接点以及操作检测电路。

公开(公告)号：US20250023485A1

公开(公告)日：2025-01-16

申请号：US18674928

申请日：2024-05-27

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masashi AKAHANE

IPC: H02M7/217 ,  H02M1/00

Abstract: Provided is a circuit apparatus including a power conversion circuit, and a control circuit which controls the power conversion circuit, in which the power conversion circuit includes a control terminal to which a control signal from the control circuit is input, an output terminal from which an output signal is output to the control circuit, and a data identification unit which identifies an input data signal input to the output terminal. A first superimposed signal in which the output signal and the input data signal are superimposed on each other may be input to the data identification unit, and the data identification unit may identify the input data signal based on the first superimposed signal and the output signal.

公开(公告)号：US20230006656A1

公开(公告)日：2023-01-05

申请号：US17751115

申请日：2022-05-23

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masashi AKAHANE ,  Taizo ASANO

IPC: H03K3/012 ,  H03K17/60

Abstract: An integrated circuit, including: a first current source; a second current source provided in parallel to the first current source; a first resistor with one end coupled to an output of the first current source; a first bipolar transistor that is diode-connected and is coupled to the other end of the first resistor; a second bipolar transistor that is diode-connected and is coupled to an output of the second current source; a second resistor coupled to the second bipolar transistor; and an output circuit configured to output a voltage based on a first voltage outputted from the first current source and a second voltage outputted from the second current source.