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    Glitch-free clock switching circuit using Muller C-elements
    2.
    发明授权
    Glitch-free clock switching circuit using Muller C-elements 有权
    无毛刺时钟切换电路使用Muller C元件

    公开(公告)号：US09490789B1

    公开(公告)日：2016-11-08

    申请号：US15139337

    申请日：2016-04-27

    申请人： FREESCALE SEMICONDUCTOR, INC.

    发明人： Chaoxuan Tian ,  Zhihong Cheng ,  Zhiling Sui

    IPC分类号： H03K19/00 ,  H03K5/135 ,  H03K19/20 ,  H03K19/003 ,  H03K19/096 ,  H03K5/00

    CPC分类号： H03K5/135 ,  H03K19/00315 ,  H03K19/096 ,  H03K19/20 ,  H03K2005/00013

    摘要： A clock switching circuit includes first and second clock lines, first and second selection lines, and first through fourth Muller C-elements. The Muller C-elements are connected to the clock and selection lines and first and second logic gates. First and second delay cells are connected to the clock lines and the second and fourth Muller C-elements. A first AND gate is connected to the first clock line, the first Muller C-element, and the first delay cell. A second AND gate is connected to the second delay cell, the third Muller C-element, and the second clock line, and an OR gate is connected to the first and second AND gates.

    摘要翻译： 时钟切换电路包括第一和第二时钟线，第一和第二选择线以及第一至第四穆勒C元件。 Muller C元件连接到时钟和选择线以及第一和第二逻辑门。 第一和第二延迟单元连接到时钟线和第二和第四Muller C元件。 第一AND门连接到第一时钟线，第一Muller C元件和第一延迟单元。 第二AND门连接到第二延迟单元，第三Muller C元件和第二时钟线，OR门连接到第一AND门和第二AND门。

    DEMODULATING FREQUENCY SHIFT KEYING MODULATED INPUT SIGNAL
    4.
    发明申请
    DEMODULATING FREQUENCY SHIFT KEYING MODULATED INPUT SIGNAL 有权
    调制频移键控调制输入信号

    公开(公告)号：US20160285658A1

    公开(公告)日：2016-09-29

    申请号：US14867014

    申请日：2015-09-28

    申请人： Freescale Semiconductor, Inc.

    发明人： Zhiling Sui ,  Zhijun Chen ,  Zhihong Cheng ,  Jiangtao Pan

    IPC分类号： H04L27/156 ,  H04L7/00 ,  H04W56/00

    CPC分类号： H04L27/1563 ,  H04L7/0087 ,  H04L27/16 ,  H04W56/0045

    摘要： A method of demodulating an FSK modulated input signal whose frequency varies between first and second frequencies. The input signal is delayed by a plurality of cycles, providing a second signal. A succession of phase reference signals having respective incrementally greater phase delays relative to the input signal are provided. Samples of the phase reference signals are taken at intervals determined by the second signal. A transition between the first and second frequencies is detected when the relative values of the samples of the phase reference signals remain constant during a plurality of intervals after varying. A high speed clock is not required to perform the demodulation.

    摘要翻译： 解调频率在第一和第二频率之间变化的FSK调制输入信号的方法。 输入信号被延迟多个周期，提供第二信号。 提供了一系列相位参考信号，其相对于输入信号具有相应的逐渐增大的相位延迟。 相位参考信号的采样以由第二信号确定的间隔进行。 当相位参考信号的样本的相对值在变化后的多个间隔期间保持恒定时，检测第一和第二频率之间的转变。 不需要高速时钟进行解调。