-
公开(公告)号：US20230088396A1
公开(公告)日：2023-03-23
申请号：US17994131
申请日：2022-11-25
Applicant: FUJI ELECTRIC CO., LTD.
Inventor： Hiroaki ICHIKAWA
Abstract: A drive device for driving a voltage-controlled semiconductor element. The drive device includes: a drive circuit connected to the gate of the semiconductor element via a gate resistor; a delay circuit connected to the drive circuit, for delaying a drive signal output from the drive circuit until a gate voltage of the semiconductor element enters a Miller effect period, which is a period during which the gate voltage transitionally changes, the gate voltage having temperature dependency on a chip temperature of the semiconductor element; a one-shot circuit connected to the delay circuit, for outputting a pulse signal with a pulse width shorter than the Miller effect period; a comparator that compares the gate voltage with a reference voltage; and an AND circuit that outputs an overheat detection signal in response to the gate voltage exceeding the reference voltage.
-
公开(公告)号：US20170027074A1
公开(公告)日：2017-01-26
申请号：US15288137
申请日：2016-10-07
Applicant: FUJI ELECTRIC CO., LTD.
Inventor： Hiroaki ICHIKAWA
IPC: H05K7/02 , H02B1/20 , H01L23/538 , H01L23/50 , H01L25/18
CPC classification number: H05K7/026 , H01L23/49844 , H01L23/50 , H01L23/5383 , H01L23/5384 , H01L25/07 , H01L25/115 , H01L25/18 , H01L2924/0002 , H02B1/205 , H02M7/003 , H05K7/06 , H05K2201/10272 , H01L2924/00
Abstract: A semiconductor device, including a plurality of semiconductor modules, each including a semiconductor element, a main terminal and a wiring portion that connects the semiconductor element and the main terminal, and at least one busbar that each includes a terminal portion, and a plurality of attachment portions, the attachment portions being respectively connected to the main terminals of the semiconductor modules, such that the at least one busbar connects the semiconductor modules in parallel. The largest resistance among all resistances between the terminal portion and each of the attachment portions in each busbar is 10% or less of a resistance of the wiring portion in each semiconductor module. The largest inductance among all inductances between the terminal portion and each of the attachment portions in each busbar is 10% or less of an inductance of the wiring portion in each semiconductor module.
Abstract translation: 一种半导体器件，包括多个半导体模块，每个半导体模块包括半导体元件，主端子和连接半导体元件和主端子的布线部分，以及每个包括端子部分的至少一个母线，以及多个 安装部分分别连接到半导体模块的主端子，使得至少一个母线并联连接半导体模块。 每个母线中的端子部分和每个连接部分之间的所有电阻之间的最大电阻为每个半导体模块中的布线部分的电阻的10％或更小。 每个母线中的端子部分和每个连接部分之间的所有电感中的最大电感为每个半导体模块中的布线部分的电感的10％或更小。
-
公开(公告)号：US20240321834A1
公开(公告)日：2024-09-26
申请号：US18734915
申请日：2024-06-05
Applicant: FUJI ELECTRIC CO., LTD.
Inventor： Mitsuhiro KAKEFU , Hiroaki ICHIKAWA
IPC: H01L25/07 , H01L23/00 , H01L23/498 , H01L29/739 , H01L29/861
CPC classification number: H01L25/072 , H01L23/49844 , H01L24/48 , H01L29/7393 , H01L29/861 , H01L2224/48225
Abstract: A semiconductor device having a semiconductor unit including: a first arm part that includes first and second semiconductor chips respectively having first and second main electrodes, a first circuit pattern on which the first and second semiconductor chips are disposed, a second circuit pattern, a first main current wire connecting the first main electrode and second circuit pattern, and a second main current wire connecting the second main electrode and the second circuit pattern; and a second arm part that includes third and fourth semiconductor chips respectively having third and fourth main electrodes and being disposed on the second circuit pattern, a third circuit pattern, a third main current wire connecting the third main electrode and the third circuit pattern, and a fourth main current wire connecting the fourth main electrode and the third circuit pattern. Each semiconductor chip is an IGBT or MOSFET.
-
公开(公告)号：US20230282622A1
公开(公告)日：2023-09-07
申请号：US18316783
申请日：2023-05-12
Applicant: FUJI ELECTRIC CO., LTD.
Inventor： Mitsuhiro KAKEFU , Hiroaki ICHIKAWA
IPC: H01L25/07 , H01L23/00 , H01L29/861 , H01L23/498 , H01L29/739
CPC classification number: H01L25/072 , H01L23/49844 , H01L24/48 , H01L29/7393 , H01L29/861 , H01L2224/48225
Abstract: A semiconductor device including a semiconductor unit that has a first arm part, which includes: first and second semiconductor chips having first and second control electrodes on their front surfaces, a first circuit pattern where the first and second semiconductor chips are disposed, a second circuit pattern to which the first and second control electrodes are connected, and a first control wire electrically connecting the first and second control electrodes and the second circuit pattern sequentially in a direction; and a second arm part, which includes third and fourth semiconductor chips having third and fourth control electrodes on their front surfaces, a third circuit pattern where the third and fourth semiconductor chips are disposed, a fourth circuit pattern to which the third and fourth control electrodes are connected, and a second control wire electrically connecting the third and fourth control electrodes and the fourth circuit pattern sequentially in the direction.
-
公开(公告)号：US20210143132A1
公开(公告)日：2021-05-13
申请号：US17153957
申请日：2021-01-21
Applicant: FUJI ELECTRIC CO., LTD.
Inventor： Mitsuhiro KAKEFU , Hiroaki ICHIKAWA
IPC: H01L25/07 , H01L23/00 , H01L29/739 , H01L29/861 , H01L23/498
Abstract: A semiconductor device, having a first semiconductor chip including a first side portion at a front surface thereof and a first control electrode formed in the first side portion, a second semiconductor chip including a second side portion at a front surface thereof and a second control electrode formed in the second side portion, a first circuit pattern, on which the first semiconductor chip and the second semiconductor chip are disposed, a second circuit pattern, and a first control wire electrically connecting the first control electrode, the second control electrode, and the second circuit pattern. The first side portion and the second side portion are aligned. The first control electrode and the second control electrode are aligned. The second circuit pattern are aligned with the first control electrode and the second control electrode.
-
Patent Agency Ranking
公开(公告)号：US20150270786A1
公开(公告)日：2015-09-24
申请号：US14730760
申请日：2015-06-04
Applicant: FUJI ELECTRIC CO., LTD.
Inventor： Shuangching CHEN , Hiroaki ICHIKAWA
IPC: H02M7/537
CPC classification number: H02M7/537 , H01L2224/0603 , H01L2924/19107 , H02M7/003 , H02M7/487
Abstract: A semiconductor device can include an insulating substrate on which at least four semiconductor elements forming a three-level power conversion circuit are mounted, a base plate on which the insulating substrate is provided, a positive conductor plate with a positive DC potential which is connected to one semiconductor element among the semiconductor elements; a negative conductor plate with a negative DC potential which is connected to another semiconductor element among the semiconductor elements and an intermediate potential conductor plate with an intermediate potential which is connected to the remaining two semiconductor elements among the semiconductor elements. The positive conductor plate, the negative conductor plate, and the intermediate potential conductor plate are provided on the base plate. The positive conductor plate and the negative conductor plate are arranged close to the intermediate potential conductor plate so as to face the intermediate potential conductor plate.
Abstract translation: 半导体器件可以包括其上安装有形成三电平电力转换电路的至少四个半导体元件的绝缘基板，设置绝缘基板的基板，具有正直流电位的正导体板，其与 半导体元件中的一个半导体元件; 连接到半导体元件中的另一半导体元件的负直流电位的负极导体板和与半导体元件中的剩余的两个半导体元件连接的具有中间电位的中间电位导体板。 正极导体板，负极导体板和中间电位导体板设置在基板上。 正导体板和负极导体板以与中间电位导体板相对的方式配置在中间电位导体板附近。
-
公开(公告)号：US20210143093A1
公开(公告)日：2021-05-13
申请号：US17155687
申请日：2021-01-22
Applicant: FUJI ELECTRIC CO., LTD.
Inventor： Hiroaki ICHIKAWA
IPC: H01L23/498 , H01L25/07 , H01L25/18 , H01L23/00
Abstract: A semiconductor device having an arm block. The arm block includes a first circuit pattern that, in a plan view of the semiconductor device, has a recess formed thereon that extends inward from a side thereof, the recess forming a disposition area of the semiconductor device, a second circuit pattern having at least a part disposed in the disposition area, and a plurality of semiconductor chips formed on the first circuit pattern. Each semiconductor chip has a positive electrode on a back surface thereof, and a control electrode and a negative electrode on a front surface thereof, the negative electrode being electrically connected to the second circuit pattern by a wiring member.
-
公开(公告)号：US20140218991A1
公开(公告)日：2014-08-07
申请号：US14157025
申请日：2014-01-16
Applicant: FUJI ELECTRIC CO., LTD.
Inventor： Shuangching CHEN , Hiroaki ICHIKAWA
CPC classification number: H02M7/537 , H01L23/36 , H01L23/3735 , H01L23/49811 , H01L25/072 , H01L2224/48137 , H01L2224/49175 , H01L2924/1305 , H01L2924/13055 , H01L2924/19107 , H02M7/003 , H02M7/487 , H01L2924/00
Abstract: In some aspects of the invention, multiple insulating substrates each mounting thereon at least one each of at least four semiconductor devices that form at least one of three-level electric power inverter circuits and a base plate on the one surface of which a plurality of the insulating plates are arranged are provided. On the one surface of the base plate, at least four regions are established and multiple insulating substrates are arranged to be distributed so that at least one each of the at least four semiconductor devices is arranged in each of the four regions established on the base plate. This can make the semiconductor devices arranged to be distributed so that heat generating sections determined according to the operation mode of the semiconductor system comes to be partial to disperse generated heat, by which a semiconductor system is provided which can enhance heat dispersion efficiency.
Abstract translation: 在本发明的一些方面，多个绝缘基板各自安装有至少四个半导体器件中的至少一个，其形成三电平电力逆变器电路和基板中的至少一个，在其一个表面上具有多个 设置绝缘板。 在基板的一个表面上，建立至少四个区域，并且布置多个绝缘基板以分布，使得至少四个半导体器件中的至少一个设置在建立在基板上的四个区域中的每一个中 。 这可以使得半导体器件被布置成分布，使得根据半导体系统的操作模式确定的发热部分将部分地分散产生的热量，由此提供可以提高散热效率的半导体系统。
-
公开(公告)号：US20250070057A1
公开(公告)日：2025-02-27
申请号：US18756112
申请日：2024-06-27
Applicant: FUJI ELECTRIC CO., LTD.
Inventor： Hiroaki ICHIKAWA
IPC: H01L23/62 , H01L23/00 , H01L23/057 , H01L23/31 , H01L23/36 , H01L23/538 , H02M7/539 , H03K17/08
Abstract: A semiconductor device, having: a circuit board, including a wiring board and a semiconductor element disposed on a first surface of the wiring board; a case having a hollow portion housing the circuit board; and a first conductive terminal and a second conductive terminal attached to the case, each of the first conductive terminal and the second conductive terminal having an inner connection portion exposed to the hollow portion of the case. The inner connection portions have a first gap therebetween in the hollow portion of the case. The first conductive terminal and the second conductive terminal each have a discharge portion facing each other across a second gap narrower than the first gap. The discharge portion of the first conductive terminal and the discharge portion of the second conductive terminal protrude to a position away from other members.
-
公开(公告)号：US20230096381A1
公开(公告)日：2023-03-30
申请号：US17878800
申请日：2022-08-01
Applicant: Fuji Electric Co., Ltd.
Inventor： Hiroaki ICHIKAWA
IPC: H01L23/367 , H01L23/047 , H01L23/373 , H01L23/00 , H01L25/07 , H01L25/18 , H01L21/48
Abstract: A semiconductor device includes: an electrically conductive plate; a semiconductor chip on the electrically conductive plate, the semiconductor chip having a front main electrode on a front surface thereof and a back main electrode on a back surface thereof, the back main electrode being bonded to the electrically conductive plate; and a heat radiating member that is bonded to the front main electrode via a conductive adhesive.
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.037 seconds)
