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    Method and apparatus for aligning multiple outputs of an FPGA
    1.
    发明授权
    Method and apparatus for aligning multiple outputs of an FPGA 有权

    公开(公告)号：US07467056B2

    公开(公告)日：2008-12-16

    申请号：US11716187

    申请日：2007-03-09

    申请人： Eric Maniloff ,  Ronald Gagnon ,  Blake Toplis

    发明人： Eric Maniloff ,  Ronald Gagnon ,  Blake Toplis

    IPC分类号： H04B13/00

    CPC分类号： H03K19/1731 ,  H03K19/17744 ,  H04L25/14

    摘要： Each data lane connected to a FPGA and forming part of a SFI channel may be trained independently to enable the outputs from the FPGA to be aligned. In operation, a known fixed pattern is repeated on each of the data lanes with the exception of the data lane being trained. The short fixed pattern is smaller than an SERDES capture range so that the SERDES may temporarily lock onto the short fixed pattern for all data lanes other than the lane being trained. Training data is then transmitted on the lane being trained and the preskew delay for that lane is adjusted until the receiving component indicates that the lanes are aligned. This process may iterate to find acceptable preskew delay values for all lanes. By training the lanes one at a time and using a short repeating pattern on the untrained lanes, the SERDES may register that the untrained lanes are operating correctly so that the feedback from the SERDES is related only to the lane being trained.

    Method and apparatus for aligning multiple outputs of an FPGA
    2.
    发明申请
    Method and apparatus for aligning multiple outputs of an FPGA 有权
    用于对准FPGA的多个输出的方法和装置

    公开(公告)号：US20080222594A1

    公开(公告)日：2008-09-11

    申请号：US11716187

    申请日：2007-03-09

    申请人： Eric Maniloff ,  Ronald Gagnon ,  Blake Toplis

    发明人： Eric Maniloff ,  Ronald Gagnon ,  Blake Toplis

    IPC分类号： H03K17/693

    CPC分类号： H03K19/1731 ,  H03K19/17744 ,  H04L25/14

    摘要： Each data lane connected to a FPGA and forming part of a SFI channel may be trained independently to enable the outputs from the FPGA to be aligned. In operation, a known fixed pattern is repeated on each of the data lanes with the exception of the data lane being trained. The short fixed pattern is smaller than an SERDES capture range so that the SERDES may temporarily lock onto the short fixed pattern for all data lanes other than the lane being trained. Training data is then transmitted on the lane being trained and the preskew delay for that lane is adjusted until the receiving component indicates that the lanes are aligned. This process may iterate to find acceptable preskew delay values for all lanes. By training the lanes one at a time and using a short repeating pattern on the untrained lanes, the SERDES may register that the untrained lanes are operating correctly so that the feedback from the SERDES is related only to the lane being trained.

    摘要翻译： 可以独立地训练连接到FPGA并形成SFI通道的一部分的每个数据通道，以使来自FPGA的输出能够对准。 在操作中，除了正在训练的数据通道之外，在每个数据通道上重复已知的固定模式。 短的固定模式小于SERDES捕获范围，以便SERDES可能暂时锁定到除被训练的通道之外的所有数据通道的短固定模式。 然后训练数据在被训练的车道上传送，并且调整该车道的预定时延，直到接收组件指示车道对齐。 该过程可以迭代以找到所有车道的可接受的前置时间延迟值。 通过一次训练车道并在未经训练的车道上使用短暂的重复模式，SERDES可以注册未经训练的车道正常运行，以便来自SERDES的反馈仅与被训练的车道相关。