公开(公告)号：US10466413B2

公开(公告)日：2019-11-05

申请号：US15607717

申请日：2017-05-30

Applicant: Electronics and Telecommunications Research Institute

Inventor： Gyungock Kim ,  Hyundai Park ,  In Gyoo Kim ,  Sang Hoon Kim ,  Ki Seok Jang ,  Sang Gi Kim ,  Jiho Joo ,  Yongseok Choi ,  Hyuk Je Kwon ,  Jaegyu Park ,  Sun Ae Kim ,  Jin Hyuk Oh ,  Myung joon Kwack

IPC: G02B6/12 ,  H01L31/167 ,  G02B6/42 ,  G02B6/13 ,  H01L21/762 ,  H01L27/15

Abstract: Disclosed are an optical input/output device and an opto-electronic system including the same. The device includes a bulk silicon substrate, at least one vertical-input light detection element monolithically integrated on a portion of the bulk silicon substrate, and at least one vertical-output light source element monolithically integrated on another portion of the bulk silicon substrate adjacent to the vertical-input light detection element. The vertical-output light source element includes a III-V compound semiconductor light source active layer combined with the bulk silicon substrate by a wafer bonding method.

公开(公告)号：US10168474B2

公开(公告)日：2019-01-01

申请号：US15607726

申请日：2017-05-30

Applicant: Electronics and Telecommunications Research Institute

Inventor： Gyungock Kim ,  Hyundai Park ,  In Gyoo Kim ,  Sang Hoon Kim ,  Ki Seok Jang ,  Sang Gi Kim ,  Jiho Joo ,  Yongseok Choi ,  Hyuk Je Kwon ,  Jaegyu Park ,  Sun Ae Kim ,  Jin Hyuk Oh ,  myung joon Kwack

IPC: G02B6/12 ,  G02B6/42 ,  G02B6/13 ,  H01L21/762 ,  H01L27/15 ,  H01L31/167

Abstract: Disclosed are an optical input/output device and an opto-electronic system including the same. The device includes a bulk silicon substrate, at least one vertical-input light detection element monolithically integrated on a portion of the bulk silicon substrate, and at least one vertical-output light source element monolithically integrated on another portion of the bulk silicon substrate adjacent to the vertical-input light detection element. The vertical-output light source element includes a III-V compound semiconductor light source active layer combined with the bulk silicon substrate by a wafer bonding method.

公开(公告)号：US09690042B2

公开(公告)日：2017-06-27

申请号：US14062454

申请日：2013-10-24

Applicant: Electronics and Telecommunications Research Institute

Inventor： Gyungock Kim ,  Hyundai Park ,  In Gyoo Kim ,  Sang Hoon Kim ,  Ki Seok Jang ,  Sang Gi Kim ,  Jiho Joo ,  Yongseok Choi ,  Hyuk Je Kwon ,  Jaegyu Park ,  Sun Ae Kim ,  Jin Hyuk Oh ,  Myung Joon Kwack

IPC: H01L27/15 ,  H01L31/153 ,  G02B6/12 ,  G02B6/13 ,  G02B6/42 ,  H01L21/762

CPC classification number: G02B6/12004 ,  G02B6/13 ,  G02B6/4206 ,  G02B6/4214 ,  H01L21/762 ,  H01L27/15 ,  H01L31/167

Abstract: Disclosed are an optical input/output device and an opto-electronic system including the same. The device includes a bulk silicon substrate, at least one vertical-input light detection element monolithically integrated on a portion of the bulk silicon substrate, and at least one vertical-output light source element monolithically integrated on another portion of the bulk silicon substrate adjacent to the vertical-input light detection element. The vertical-output light source element includes a III-V compound semiconductor light source active layer combined with the bulk silicon substrate by a wafer bonding method.

公开(公告)号：US12019568B2

公开(公告)日：2024-06-25

申请号：US17518823

申请日：2021-11-04

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Yongseok Choi

IPC: G06F13/16 ,  G06F13/42 ,  G06F15/177 ,  G06F18/214

CPC classification number: G06F13/1673 ,  G06F13/1689 ,  G06F13/4282 ,  G06F15/177 ,  G06F18/214

Abstract: Provided are serial communication method and system for memory access. The serial communication system for memory access includes a processor-side processor that receives a memory transaction from a processor and converts the memory transaction into a packet according to a predetermined phase to serially transmit the packet; a memory-side processor that receives the serially transmitted packet according to the predetermined phase and converts the packet into the memory transaction to access a memory, wherein the predetermined phase includes a channel establishment phase, a flow control initialization phase, and a memory transaction phase.

公开(公告)号：US11836106B2

公开(公告)日：2023-12-05

申请号：US17559248

申请日：2021-12-22

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Yongseok Choi

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0038

Abstract: Provided are a serial communication device and a serial communication system for a memory access. The serial communication device for a memory access may include: a system-on-chip (SoC) bus interface receiving a request transaction from a hardware acceleration device; a master protocol processor converting a request transaction received through the SoC bus interface into a packet according to a predetermined packet protocol; and a serial transceiver serial-transmitting the packet.

公开(公告)号：US08909843B1

公开(公告)日：2014-12-09

申请号：US14037147

申请日：2013-09-25

Applicant: Electronics and Telecommunications Research Institute

Inventor： Yongseok Choi

IPC: G06F13/38 ,  G06F11/20 ,  G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4022 ,  G06F11/2007 ,  G06F13/385

Abstract: A peripheral component interconnect (PCI) express switch apparatus and a method of controlling a connection thereof are provided. In this apparatus, a first virtual bridge is connected to a computer system through a first PCI express port to perform data transmission and reception according to a PCI method with an external device, and a second virtual bridge is connected to an external device through the first virtual bridge and a second PCI express port and enables the external device to perform data transmission and reception with the computer system and according to the PCI method by cooperating with the first virtual bridge. A first cable matching device is connected to the first virtual bridge. Further, a second cable matching device is connected to the second virtual bridge and is connected to the first cable matching device through a PCI cable. In addition, the PCI cable has a cable corresponding to lanes of the number of more than that of a maximum lane in which the first virtual bridge and the second virtual bridge perform data transmission and reception.

Abstract translation: 提供外围部件互连（PCI）快速开关装置和控制其连接的方法。 在该装置中，第一虚拟桥接器通过第一PCI Express端口连接到计算机系统，以根据与外部设备的PCI方法进行数据发送和接收，并且第二虚拟桥接器通过第一PCI Express端口连接到外部设备 虚拟桥和第二PCI Express端口，并使外部设备能够与计算机系统进行数据传输和接收，并根据PCI方法通过与第一虚拟桥协作。 第一电缆匹配装置连接到第一虚拟桥。 此外，第二电缆匹配装置连接到第二虚拟电桥，并通过PCI电缆连接到第一电缆匹配装置。 此外，PCI电缆具有与第一虚拟桥和第二虚拟桥进行数据发送和接收的最大通道数相比更多的通道的电缆。