APPARATUS AND METHOD OF GENERATING NETWORK CLOCK REFERENCE (NCR) PACKET FOR ACQUIRING NETWORK SYNCHRONIZATION IN TWO-WAY SATELLITE COMMUNICATION SYSTEM
    4.
    发明申请
    APPARATUS AND METHOD OF GENERATING NETWORK CLOCK REFERENCE (NCR) PACKET FOR ACQUIRING NETWORK SYNCHRONIZATION IN TWO-WAY SATELLITE COMMUNICATION SYSTEM 审中-公开
    用于在两路卫星通信系统中获取网络同步的网络时钟参考(NCR)分组的装置和方法

    公开(公告)号:US20160242136A1

    公开(公告)日:2016-08-18

    申请号:US15043707

    申请日:2016-02-15

    Inventor: Soo Yeob JUNG

    CPC classification number: H04W56/0045 H04W56/001

    Abstract: An apparatus for generating a network clock reference (NCR) packet for acquiring network synchronization between satellite communication devices in two-way satellite communication system, the apparatus including a clock reference determiner configured to determine an NCR based on a trigger signal with respect to a start of a first frame, a synchronization compensator configured to determine a synchronization compensation value by reflecting frame variable length information from the first frame to a second frame into which an NCR packet is to be inserted, and a packet generator configured to generate the NCR packet by combining the NCR and the synchronization compensation value, is provided.

    Abstract translation: 一种用于生成用于在双向卫星通信系统中获取卫星通信设备之间的网络同步的网络时钟参考(NCR)分组的装置,所述装置包括:时钟参考确定器,被配置为基于相对于开始的触发信号来确定NCR 配置为通过将来自第一帧的帧可变长度信息反映到要插入NCR分组的第二帧来确定同步补偿值的同步补偿器,以及被配置为通过以下步骤生成NCR分组的分组生成器: 提供了NCR和同步补偿值的组合。

    METHOD AND APPARATUS FOR TRANSMITTING SIGNALS USING  FREQUENCY HOPPING

    公开(公告)号:US20240214115A1

    公开(公告)日:2024-06-27

    申请号:US18396528

    申请日:2023-12-26

    CPC classification number: H04L1/0061 H04L1/0071 H04L5/0012 H04L27/2605

    Abstract: A transmission device in a satellite IoT system may comprise: a CRC value generator that receives first data and generates and outputs a payload CRC value; a forward error correction encoder that receives second data consisting of the first data and the payload CRC value from the CRC value generator, and performs forward error correction coding on the second data; an interleaver that receives third data consisting of the forward error correction coded first data and the payload CRC value from the forward error correction encoder, and outputs interleaved payload blocks by performing cyclic shifts on the forward error correction coded first data based on offsets; and a frequency hopping unit that receives the interleaved payload blocks from the interleaver, and generates and transmits payload blocks frequency-hopped according to a hopping sequence.

    SYSTEM AND METHOD FOR SYNCHRONIZATION BETWEEN DIGITAL-TO-ANALOG CONVERTERS (DACs) FOR HIGH SPEED SIGNAL PROCESSING
    10.
    发明申请
    SYSTEM AND METHOD FOR SYNCHRONIZATION BETWEEN DIGITAL-TO-ANALOG CONVERTERS (DACs) FOR HIGH SPEED SIGNAL PROCESSING 有权
    用于高速信号处理的数字到模拟转换器(DAC)之间的同步的系统和方法

    公开(公告)号:US20150061909A1

    公开(公告)日:2015-03-05

    申请号:US14301753

    申请日:2014-06-11

    CPC classification number: H03M1/662 H03M1/0624 H03M1/66

    Abstract: Provided is a system and method for synchronization between digital-to-analog converters (DAC) for high speed signal processing. A synchronization method of a multi-DAC apparatus may include: inputting a clock to a multiplexer (MUX) DAC; dividing the clock into a first clock and a second clock; transferring a phase difference between the first clock and the second clock to a D flip-flop; and synchronizing the first clock and the second clock by processing the phase difference.

    Abstract translation: 提供了用于高速信号处理的数模转换器(DAC)之间的同步的系统和方法。 多DAC装置的同步方法可以包括:将时钟输入到多路复用器(MUX)DAC; 将时钟分为第一时钟和第二时钟; 将第一时钟和第二时钟之间的相位差传送到D触发器; 以及通过处理所述相位差来同步所述第一时钟和所述第二时钟。

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