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    INTERFACE CIRCUIT FOR TRANSMITTING AND RECEIVING SIGNALS BETWEEN ELECTRONIC DEVICES, AND SEMICONDUCTOR MEMORY CHIP AND OPERATION PROCESSING DEVICE INCLUDING THE SAME
    2.
    发明申请
    INTERFACE CIRCUIT FOR TRANSMITTING AND RECEIVING SIGNALS BETWEEN ELECTRONIC DEVICES, AND SEMICONDUCTOR MEMORY CHIP AND OPERATION PROCESSING DEVICE INCLUDING THE SAME 审中-公开
    用于发送和接收电子设备之间的信号的接口电路和包括其的半导体存储器芯片和操作处理设备

    公开(公告)号：US20150207565A1

    公开(公告)日：2015-07-23

    申请号：US14595754

    申请日：2015-01-13

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Hyuk Je KWON ,  Yongseok CHOI ,  Gyungock KIM

    IPC: H04B10/2575

    CPC classification number: H04B10/801 ,  H04B10/2503

    Abstract: An interface circuit configured to transmit and receive signals between electronic devices is provided. The interface circuit includes an optical connection protocol manager configured to serialize a parallel transmission packet electrical signal generated based on output data to generate a serialized transmission packet electrical signal, parallelize a serial reception packet electrical signal to generate a parallelized reception packet electrical signal, and parse the parallelized reception packet electrical signal according to whether there is an error in the parallelized reception packet electrical signal to generate input data; and an electro-optical converter configured to convert the serialized transmission packet electrical signal into a transmission packet optical signal to output the transmission packet optical signal, receive a reception packet optical signal, and convert the reception packet optical signal into the serial reception packet electrical signal to provide the serial reception packet electrical signal to the optical connection protocol manager.

    Abstract translation: 提供了一种配置成在电子设备之间发送和接收信号的接口电路。 该接口电路包括：光连接协议管理器，被配置为串行化基于输出数据生成的并行传输分组电信号，以产生串行化的传输分组电信号;并行化串行接收分组电信号以产生并行接收分组电信号，并解析 并行接收分组电信号，根据并行接收分组电信号是否存在错误以产生输入数据; 以及电光转换器，被配置为将串行化的发送分组电信号转换为发送分组光信号，以输出发送分组光信号，接收接收分组光信号，并将接收分组光信号转换为串行接收分组电信号 以将串行接收分组电信号提供给光学连接协议管理器。

    METHOD OF DECODING RESPONSE SIGNAL FROM RADIO FREQUENCY IDENTIFICATION
    3.
    发明申请
    METHOD OF DECODING RESPONSE SIGNAL FROM RADIO FREQUENCY IDENTIFICATION 审中-公开
    从无线电频率识别中解码响应信号的方法

    公开(公告)号：US20140132397A1

    公开(公告)日：2014-05-15

    申请号：US13869583

    申请日：2013-04-24

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Hyuk Je KWON

    IPC: G06K7/10

    CPC classification number: G06K7/10009 ,  H04L7/042

    Abstract: A data decoder may include a subcarrier removing unit configured to remove a subcarrier from first data to generate second data, a preamble detecting unit configured to detect a preamble for the second data, and a decoding unit configured to decode the second data based on the detected preamble.

    Abstract translation: 数据解码器可以包括：副载波去除单元，被配置为从第一数据去除副载波以产生第二数据;前置码检测单元，被配置为检测第二数据的前同步码;以及解码单元，被配置为基于检测到的第二数据解码第二数据 前言。

    PACKET TRANSMISSION AND RECEPTION SYSTEM, APPARATUS, AND METHOD
    4.
    发明申请
    PACKET TRANSMISSION AND RECEPTION SYSTEM, APPARATUS, AND METHOD 有权
    分组传输和接收系统，装置和方法

    公开(公告)号：US20160065331A1

    公开(公告)日：2016-03-03

    申请号：US14800603

    申请日：2015-07-15

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Yong Seok CHOI ,  Hyuk Je KWON

    IPC: H04L1/18 ,  G06F13/42 ,  G06F11/10

    CPC classification number: H04L1/1858 ,  G06F11/1004 ,  G06F13/4282

    Abstract: Provided are a packet transmission and reception system, apparatus, and method. The packet transmission and reception system for distributing and transmitting data through a plurality of multi-lanes includes a first transmission and reception apparatus configured to include a plurality of first physical lanes and a plurality of first logical lanes connected to the plurality of first physical lanes, and a second transmission and reception apparatus configured to include a plurality of second physical lanes and a plurality of second logical lanes connected to the plurality of second physical lanes.

    Abstract translation: 提供了一种分组发送和接收系统，装置和方法。 用于通过多个多通道分发和发送数据的分组发送和接收系统包括：第一发送和接收装置，被配置为包括连接到多个第一物理通道的多个第一物理通道和多个第一逻辑通道， 以及第二发送和接收装置，被配置为包括连接到所述多个第二物理通道的多个第二物理通道和多个第二逻辑通道。

    MEMORY CONTROL SYSTEM AND MEMORY INTERFACE METHOD USING THE SAME
    5.
    发明申请
    MEMORY CONTROL SYSTEM AND MEMORY INTERFACE METHOD USING THE SAME 审中-公开
    存储器控制系统和使用其的存储器接口方法

    公开(公告)号：US20140372669A1

    公开(公告)日：2014-12-18

    申请号：US14039884

    申请日：2013-09-27

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Hyuk Je KWON ,  Youngseok Choi

    IPC: G06F12/02 ,  G06F9/30 ,  G11C11/406

    CPC classification number: G06F12/0246 ,  G06F13/1668

    Abstract: A memory control system includes: a memory that stores data; a memory controller that controls operation of the memory by a memory control signal; and a CPU that forms a single link with the memory controller and transmits the memory control signal to the memory controller via the single link.

    Abstract translation: 存储器控制系统包括：存储数据的存储器; 存储器控制器，其通过存储器控制信号来控制存储器的操作; 以及与存储器控制器形成单个链接的CPU，并且经由单个链路将存储器控制信号发送到存储器控制器。

    HETEROGENEOUS MEMORY SYSTEM AND DATA COMMUNICATION METHOD IN THE SAME
    10.
    发明申请
    HETEROGENEOUS MEMORY SYSTEM AND DATA COMMUNICATION METHOD IN THE SAME 审中-公开
    异构存储器系统和数据通信方法

    公开(公告)号：US20160034405A1

    公开(公告)日：2016-02-04

    申请号：US14813916

    申请日：2015-07-30

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Hyuk Je KWON ,  Yong Seok CHOI

    IPC: G06F13/16 ,  G06F13/42

    CPC classification number: G06F13/1668 ,  G06F13/4282

    Abstract: Provided are a heterogeneous memory system and a data communication method in the same. The heterogeneous memory system includes a plurality of different kinds of memory cells, and a central processing unit (CPU) configured to communicate with each of the plurality of memory cells using a high-speed serial link technique. The CPU includes a CPU protocol engine that generates and packetizes command data to be transmitted to at least one of the plurality of memory cells, and each of the plurality of memory cells include a memory protocol engine configured to analyze the command data received from the CPU, and a memory controller configured to perform the corresponding operation according to the analysis result in the memory protocol engine.

    Abstract translation: 提供了异构存储器系统和数据通信方法。 异构存储器系统包括多个不同种类的存储单元，以及配置成使用高速串行链路技术与多个存储单元中的每一个进行通信的中央处理单元（CPU）。 CPU包括CPU协议引擎，其生成并分组要发送到多个存储器单元中的至少一个的命令数据，并且多个存储器单元中的每一个包括被配置为分析从CPU接收的命令数据的存储器协议引擎 以及存储器控制器，被配置为根据存储器协议引擎中的分析结果执行相应的操作。

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