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1.发明授权Method and apparatus for limiting startup inrush current for low dropout regulator 有权用于限制低压差稳压器启动浪涌电流的方法和装置公开(公告)号：US09454164B2
公开(公告)日：2016-09-27
申请号：US14020979
申请日：2013-09-09
Applicant: Dialog Semiconductor GmbH
Inventor： Ambreesh Bhattad
Abstract: A low dropout (LDO) regulator with a limited startup inrush current is disclosed. The LDO includes a power source, error amplifier, pass transistor, feedback network, and a current limit control whose input is electrically connected to the pass transistor and the electrical output of the error amplifier and whose output limits current during startup. The LDO can include a current control limit comparator including a power source, and output of the pass transistor. The LDO can also include a bypass mode current control limit comparator having a first input voltage of the error amplifier, and a second input voltage from the error amplifier.
Abstract translation: 公开了一种具有有限启动浪涌电流的低压差（LDO）调节器。 LDO包括电源，误差放大器，传输晶体管，反馈网络和电流限制控制，其输入电连接到传输晶体管和误差放大器的电输出，并且其输出在启动期间限制电流。 LDO可以包括电流控制限制比较器，其包括电源和传输晶体管的输出。 LDO还可以包括具有误差放大器的第一输入电压的旁路模式电流控制限制比较器和来自误差放大器的第二输入电压。
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2.发明申请公开(公告)号：US20160132064A1
公开(公告)日：2016-05-12
申请号：US14996705
申请日：2016-01-15
Applicant: Dialog Semiconductor GmbH
Inventor： Ambreesh Bhattad , Ludmil Nikolov
IPC: G05F1/575
CPC classification number: G05F1/575
Abstract: Circuits and methods to improve dynamic load transient performance of circuits supplying high current and having parasitic resistances are disclosed. These circuits comprise e.g. LDOs, amplifiers or buffers. The circuits and methods are characterized by including parasitic resistances, caused by bond wires, metallization of pass devices, and substrate routings, in a loop for fast transient response. Furthermore the circuits comprise a stabilization circuit within said loop and a separate pad for said loop.
Abstract translation: 公开了提供高电流并具有寄生电阻的电路的动态负载瞬变性能的电路和方法。 这些电路包括例如 LDO，放大器或缓冲器。 电路和方法的特征在于包括由接合线引起的寄生电阻，通过器件的金属化以及衬底布线，用于快速瞬态响应。 此外，电路包括在所述回路内的稳定电路和用于所述回路的单独的垫。
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公开(公告)号：US20150309520A1
公开(公告)日：2015-10-29
申请号：US14794135
申请日：2015-07-08
Applicant: Dialog Semiconductor GmbH , Dialog Semiconductor B.V.
Inventor： Ambreesh Bhattad , Ludmil Nikolov , Marinus Wilhelmus Kruiskamp
CPC classification number: G05F1/575 , G05F3/02 , H03F3/04 , H03G1/0094
Abstract: Circuits and methods to maintain a resistive voltage divider ratio during start-up of an electronic circuit comprising a feed-forward capacitor across a feedback resistor using a dynamic start-up circuit are disclosed as e.g. a LDO or an amplifier. In a preferred embodiment of the disclosure is applied to an LDO. Modification of the resistive voltage divider ratio caused by the feed-forward capacitor during start-up is prevented while the voltage level of a voltage access point of the voltage divider on the feed-forward capacitor is maintained. A start-up circuit comprises a start-up capacitor and a start-up comparator.
Abstract translation: 公开了在包括使用动态启动电路的反馈电阻器上的前馈电容器的电子电路启动期间维持电阻分压比的电路和方法。 LDO或放大器。 在本公开的优选实施例中，应用于LDO。 在保持前馈电容器的分压器的电压接入点的电压电平的同时，防止在启动期间由前馈电容器引起的电阻分压比的改变。 启动电路包括启动电容器和启动比较器。
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公开(公告)号：US20150177757A1
公开(公告)日：2015-06-25
申请号：US14147685
申请日：2014-01-06
Applicant: Dialog Semiconductor GmbH
Inventor： Ambreesh Bhattad , Frank Kronmueller , Alper Ucar , Hande Kurnaz
IPC: G05F1/575
Abstract: Methods and circuits for linearly controlling a limited, constant current during startup of LDOs, amplifiers, or DC-to-DC converters independent of load capacitor size and controlling a clean transition without glitches from a constant current (CC) mode during startup to a constant voltage (CV) mode during normal operation (CC-CV method) are disclosed. The constant current control loop and the constant voltage control loop are implemented in such a way that at the end of startup the voltage loop has taken over control and the current loop is moved far away from its active transistor region, allowing a switch of modes to occur without any nasty transitions on the output.
Abstract translation: 用于线性控制LDO，放大器或DC-DC转换器启动期间有限的恒定电流的方法和电路，与负载电容器尺寸无关，并控制清洁过渡，而不会在启动期间从恒定电流（CC）模式发生毛刺到恒定 公开了正常工作期间的电压（CV）模式（CC-CV方法）。 恒流控制回路和恒压控制回路以这样的方式实现，使得在启动结束时，电压回路已经接管并且电流回路远离其有源晶体管区域移动，允许模式切换到 在输出上没有任何令人讨厌的过渡。
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5.发明申请Apparatus and Method for a Voltage Regulator with Improved Power Supply Reduction Ratio (PSRR) with Reduced Parasitic Capacitance on Bias Signal Lines 有权具有改善的电源降低比（PSRR）的电压调节器的装置和方法，在偏置信号线上具有减少的寄生电容公开(公告)号：US20150123628A1
公开(公告)日：2015-05-07
申请号：US14073106
申请日：2013-11-06
Applicant: Dialog Semiconductor GmbH
Inventor： Ambreesh Bhattad , Ludmil Nikolov
IPC: G05F1/563
Abstract: An apparatus and method for a system with improved power supply rejection ratio (PSRR) over a wide frequency range. The improved PSRR is achieved by negating the influence of the parasitic capacitance associated with the bias lines and the introduction of a regulated power supply with embodiments associated with providing a ripple free and regulated supply. With reduction of parasitic capacitance, and providing an ENABLE switch by a pre-regulated supply, the degradation of the PSRR is achieved. The embodiments include both n-channel and p-channel MOSFETs implementations, and a positive and negative regulated power supply voltage. With the combined influence of the utilization of the VREG supply, and the lowering of battery-to-bias line capacitance using design layout and improved floor planning an improved PSRR over a wide frequency distribution is achieved.
Abstract translation: 一种在宽频率范围内具有改善的电源抑制比（PSRR）的系统的装置和方法。 改进的PSRR通过否定与偏置线相关的寄生电容的影响以及引入具有与提供无纹波和调节的电源相关联的实施例的稳压电源来实现。 通过减小寄生电容，并通过预调节电源提供ENABLE开关，可实现PSRR的降级。 这些实施例包括n沟道和p沟道MOSFET实现以及正和负调节电源电压。 随着VREG电源的利用的综合影响，以及使用设计布局和改进的平面布局降低电池对偏置线电容，实现了在宽频率分布上的改进的PSRR。
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Patent Agency Ranking
6.发明申请公开(公告)号：US20150097534A1
公开(公告)日：2015-04-09
申请号：US14052838
申请日：2013-10-14
Applicant: Dialog Semiconductor GmbH
Inventor： Ambreesh Bhattad
IPC: G05F1/46
CPC classification number: G05F1/575 , G05F1/462 , G05F1/56 , H02M1/32 , H03F3/45183 , H03F2200/555 , H03F2203/45314 , H03F2203/45636 , H03F2203/45674 , H03F2203/45676
Abstract: An overshoot reduction circuit within a low dropout voltage regulator eliminates an overshoot at an output terminal resulting from a transient fault condition occurring at an input or output terminal. The overshoot reduction circuit monitors to sense if there is a transient fault condition occurring at the input or output terminal and provides a Miller capacitance at the output terminal of a differential amplifier of the low dropout voltage regulator to prevent the output of the differential amplifier from being discharged to ground during the transient. A control loop circuit balances current within an active load of the differential amplifier to clamp the output of the differential amplifier to its normal operating point. When the transient fault condition ends, the output voltage of the differential amplifier is set such that a pass transistor of the low dropout regulator responds quickly to resume the regulation to reduce or eliminate the overshoot.
Abstract translation: 低压降稳压器内的过冲减少电路消除了由输入或输出端子发生的瞬态故障情况导致的输出端子上的过冲。 过冲减少电路监视以检测在输入或输出端子处是否存在瞬态故障状况，并在低压差稳压器的差分放大器的输出端提供米勒电容，以防止差动放大器的输出为 在短暂期间放电到地面。 控制回路电路平衡差分放大器的有效负载内的电流，将差分放大器的输出钳位到其正常工作点。 当瞬态故障状态结束时，差分放大器的输出电压被设置为使得低压差稳压器的通过晶体管快速响应以恢复调节以减少或消除过冲。
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公开(公告)号：US08981840B1
公开(公告)日：2015-03-17
申请号：US14028735
申请日：2013-09-17
Applicant: Dialog Semiconductor GmbH
Inventor： Julian Tyrrell , Ambreesh Bhattad
CPC classification number: G05F3/16 , G05F1/56 , H03K17/063 , H03K2217/0054
Abstract: A pass device configured from a common gate transistor, wherein an input voltage is applied to the source and an output at the drain is applied to a load. The input resistance of the pass device increases as the input voltage is reduced and limits the useful range of the input voltage. Increasing the gate to source voltage (Vgs) by applying a negative voltage to the gate reduces the input resistance and increases the range of operation of the pass device.
Abstract translation: 由公共栅极晶体管配置的通过器件，其中输入电压被施加到源极，并且漏极处的输出被施加到负载。 通过器件的输入电阻随着输入电压的降低而增加，并限制输入电压的有效范围。 通过向栅极施加负电压来增加栅极到源极电压（Vgs），从而减小输入电阻并增加通过器件的工作范围。
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公开(公告)号：US09798340B2
公开(公告)日：2017-10-24
申请号：US14521765
申请日：2014-10-23
Applicant: Dialog Semiconductor GmbH
Inventor： Ambreesh Bhattad , Frank Kronmueller
CPC classification number: G05F1/56 , G05F1/562 , G05F1/569 , G05F1/573 , G05F1/5735 , H02H9/001 , H02M1/36
Abstract: A circuit is provided with inrush current protection through control of the output current at start-up by a current source that does not rely on the output capacitor and which provides a smooth transition from a controlled current mode during a start-up phase to a voltage regulation mode.
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9.发明授权公开(公告)号：US09454170B2
公开(公告)日：2016-09-27
申请号：US14996705
申请日：2016-01-15
Applicant: Dialog Semiconductor GmbH
Inventor： Ambreesh Bhattad , Ludmil Nikolov
CPC classification number: G05F1/575
Abstract: Circuits and methods to improve dynamic load transient performance of circuits supplying high current and having parasitic resistances are disclosed. These circuits comprise e.g. LDOs, amplifiers or buffers. The circuits and methods are characterized by including parasitic resistances, caused by bond wires, metallization of pass devices, and substrate routings, in a loop for fast transient response. Furthermore the circuits comprise a stabilization circuit within said loop and a separate pad for said loop.
Abstract translation: 公开了提供高电流并具有寄生电阻的电路的动态负载瞬变性能的电路和方法。 这些电路包括例如 LDO，放大器或缓冲器。 电路和方法的特征在于包括由接合线引起的寄生电阻，通过器件的金属化以及衬底布线，用于快速瞬态响应。 此外，电路包括在所述回路内的稳定电路和用于所述回路的单独的垫。
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10.发明申请公开(公告)号：US20160195884A1
公开(公告)日：2016-07-07
申请号：US15072591
申请日：2016-03-17
Applicant: Dialog Semiconductor GmbH
Inventor： Ambreesh Bhattad
CPC classification number: G05F1/575 , G05F1/462 , G05F1/56 , H02M1/32 , H03F3/45183 , H03F2200/555 , H03F2203/45314 , H03F2203/45636 , H03F2203/45674 , H03F2203/45676
Abstract: An overshoot reduction circuit within a low dropout voltage regulator eliminates an overshoot at an output terminal resulting from a transient fault condition occurring at an input or output terminal. The overshoot reduction circuit monitors to sense if there is a transient fault condition occurring at the input or output terminal and provides a Miller capacitance at the output terminal of a differential amplifier of the low dropout voltage regulator to prevent the output of the differential amplifier from being discharged to ground during the transient. A control loop circuit balances current within an active load of the differential amplifier to clamp the output of the differential amplifier to its normal operating point. When the transient fault condition ends, the output voltage of the differential amplifier is set such that a pass transistor of the low dropout regulator responds quickly to resume the regulation to reduce or eliminate the overshoot.
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