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    Flash memory devices that support efficient memory locking operations and methods of operating flash memory devices
    1.
    发明授权
    Flash memory devices that support efficient memory locking operations and methods of operating flash memory devices 有权
    支持高效内存锁定操作的闪存设备和操作闪存设备的方法

    公开(公告)号：US06975547B2

    公开(公告)日：2005-12-13

    申请号：US10820245

    申请日：2004-04-06

    Applicant: Dae Seok Byeon ,  Seung-Jae Lee

    Inventor： Dae Seok Byeon ,  Seung-Jae Lee

    IPC: G06F12/00 ,  G11C7/24 ,  G11C16/22 ,  G11C7/00

    CPC classification number: G11C7/24 ,  G11C16/22

    Abstract: Flash memory devices include at least one flash memory array and an address compare circuit that is configured to indicate whether an applied row address associated with a first operation (e.g., program, erase) is within or without an unlock area of the at least one flash memory array. A control circuit is also provided. This control circuit is configured to block performance of the first operation on the flash memory array in response to detecting an indication from the address compare circuit that the applied row address is outside the unlock area of the flash memory array.

    Abstract translation: 闪存设备包括至少一个闪存阵列和地址比较电路，其被配置为指示与第一操作（例如，程序，擦除）相关联的应用行地址是否在至少一个闪存的解锁区域内 内存阵列 还提供控制电路。 响应于检测到来自地址比较电路的指示，所施加的行地址在闪存阵列的解锁区域之外，该控制电路被配置为阻止闪速存储器阵列上的第一操作的性能。

    Nonvolatile memory device and nonvolatile memory system employing same
    2.
    发明授权
    Nonvolatile memory device and nonvolatile memory system employing same 有权
    非易失性存储器件和采用它的非易失性存储器系统

    公开(公告)号：US08432741B2

    公开(公告)日：2013-04-30

    申请号：US13419732

    申请日：2012-03-14

    Applicant: Seung-Jae Lee ,  Dae-Seok Byeon ,  Hyun-Chul Ha

    Inventor： Seung-Jae Lee ,  Dae-Seok Byeon ,  Hyun-Chul Ha

    IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06

    CPC classification number: G11C16/28 ,  G11C16/0408

    Abstract: A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor through the first dummy memory cell and the second dummy memory cell. During a read-out operation mode, a dummy read-out voltage is applied to a first dummy wordline coupled to the first dummy memory cell, and to a second dummy wordline coupled to the second dummy memory cell. The dummy read-out voltage has a lower magnitude than a read-out voltage applied to an unselected memory cell during the read-out operation mode.

    Abstract translation: 非易失性存储器件包括存储单元阵列，行选择电路和电压发生器。 存储单元阵列包括第一虚拟存储单元，第二虚拟存储单元和NAND串，其包括通过第一虚拟存储单元和第二虚拟存储单元串联耦合在串选择晶体管和接地选择晶体管之间的多个存储单元 记忆单元 在读出操作模式期间，将虚拟读出电压施加到耦合到第一虚拟存储器单元的第一伪字线以及耦合到第二虚拟存储单元的第二虚拟字线。 在读出操作模式期间，虚拟读出电压具有比在未选择存储单元上施加的读出电压更低的量值。

    Nonvolatile memory device and nonvolatile memory system employing same
    3.
    发明授权
    Nonvolatile memory device and nonvolatile memory system employing same 有权
    非易失性存储器件和采用它的非易失性存储器系统

    公开(公告)号：US08154927B2

    公开(公告)日：2012-04-10

    申请号：US12868022

    申请日：2010-08-25

    Applicant: Seung-Jae Lee ,  Dae-Seok Byeon ,  Hyun-Chul Ha

    Inventor： Seung-Jae Lee ,  Dae-Seok Byeon ,  Hyun-Chul Ha

    IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06

    CPC classification number: G11C16/28 ,  G11C16/0408

    Abstract: A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor through the first dummy memory cell and the second dummy memory cell. During a read-out operation mode, a dummy read-out voltage is applied to a first dummy wordline coupled to the first dummy memory cell, and to a second dummy wordline coupled to the second dummy memory cell. The dummy read-out voltage has a lower magnitude than a read-out voltage applied to an unselected memory cell during the read-out operation mode.

    Abstract translation: 非易失性存储器件包括存储单元阵列，行选择电路和电压发生器。 存储单元阵列包括第一虚拟存储单元，第二虚拟存储单元和NAND串，其包括通过第一虚拟存储单元和第二虚拟存储单元串联耦合在串选择晶体管和接地选择晶体管之间的多个存储单元 记忆单元 在读出操作模式期间，将虚拟读出电压施加到耦合到第一虚拟存储器单元的第一伪字线以及耦合到第二虚拟存储单元的第二虚拟字线。 在读出操作模式期间，虚拟读出电压具有比在未选择存储单元上施加的读出电压更低的量值。

    Multi-level high voltage generator
    4.
    发明申请
    Multi-level high voltage generator 有权
    多级高压发生器

    公开(公告)号：US20050127981A1

    公开(公告)日：2005-06-16

    申请号：US10940808

    申请日：2004-08-24

    Applicant: Seung-Jae Lee ,  Dae-Seok Byeon

    Inventor： Seung-Jae Lee ,  Dae-Seok Byeon

    IPC: G11C16/06 ,  G11C5/14 ,  G11C16/30 ,  H02M3/07 ,  H03H11/24 ,  H03H11/26

    CPC classification number: G11C16/30 ,  G11C5/145 ,  H02M3/07 ,  H02M2001/009 ,  H03H11/245

    Abstract: A multi-level high voltage generator according to embodiments of the invention is capable of simultaneously generating high voltages of various levels by using one charge pump. The multi-level high voltage generator includes a charge pump unit, a voltage divider unit, and a pump control unit. The charge pump unit raises an input voltage applied at an input terminal to simultaneously output a number of high voltages having different levels. The voltage divider unit divides the voltages from the charge pump unit. The pump control unit operates according to an enable signal and generates pump control signals in response to a reference voltage, a control clock signal, and a divided voltage from the voltage divider unit. The charge pump unit generates the high voltages and is controlled by the pump control signals from the pump control unit.

    Abstract translation: 根据本发明的实施例的多电平高压发生器能够通过使用一个电荷泵同时产生各种电平的高电压。 多电平高压发生器包括电荷泵单元，分压器单元和泵控制单元。 电荷泵单元提高施加在输入端子处的输入电压，以同时输出具有不同电平的多个高电压。 分压器单元分离电荷泵单元的电压。 泵控制单元根据使能信号进行工作，响应于参考电压，控制时钟信号和来自分压器单元的分压产生泵控制信号。 电荷泵单元产生高电压并由来自泵控制单元的泵控制信号控制。

    Multi-level high voltage generator
    5.
    发明授权
    Multi-level high voltage generator 有权
    多级高压发生器

    公开(公告)号：US07176747B2

    公开(公告)日：2007-02-13

    申请号：US10940808

    申请日：2004-08-24

    Applicant: Seung-Jae Lee ,  Dae-Seok Byeon

    Inventor： Seung-Jae Lee ,  Dae-Seok Byeon

    IPC: G05F1/10

    CPC classification number: G11C16/30 ,  G11C5/145 ,  H02M3/07 ,  H02M2001/009 ,  H03H11/245

    Abstract: A multi-level high voltage generator according to embodiments of the invention is capable of simultaneously generating high voltages of various levels by using one charge pump. The multi-level high voltage generator includes a charge pump unit, a voltage divider unit, and a pump control unit. The charge pump unit raises an input voltage applied at an input terminal to simultaneously output a number of high voltages having different levels. The voltage divider unit divides the voltages from the charge pump unit. The pump control unit operates according to an enable signal and generates pump control signals in response to a reference voltage, a control clock signal, and a divided voltage from the voltage divider unit. The charge pump unit generates the high voltages and is controlled by the pump control signals from the pump control unit.

    Abstract translation: 根据本发明的实施例的多电平高压发生器能够通过使用一个电荷泵同时产生各种电平的高电压。 多电平高压发生器包括电荷泵单元，分压器单元和泵控制单元。 电荷泵单元提高施加在输入端子处的输入电压，以同时输出具有不同电平的多个高电压。 分压器单元分离电荷泵单元的电压。 泵控制单元根据使能信号进行工作，响应于参考电压，控制时钟信号和来自分压器单元的分压产生泵控制信号。 电荷泵单元产生高电压并由来自泵控制单元的泵控制信号控制。

    Method and apparatus for managing digital rights of secure removable media
    7.
    发明授权
    Method and apparatus for managing digital rights of secure removable media 有权
    用于管理安全可移动媒体的数字权利的方法和装置

    公开(公告)号：US08683610B2

    公开(公告)日：2014-03-25

    申请号：US13566700

    申请日：2012-08-03

    Applicant: Seung-Jae Lee ,  Te-Hyun Kim

    Inventor： Seung-Jae Lee ,  Te-Hyun Kim

    IPC: G06F7/04

    CPC classification number: H04L9/3273 ,  G06F21/10 ,  H04L9/3247 ,  H04L63/0428 ,  H04L63/10 ,  H04L63/12 ,  H04L2209/603 ,  H04L2463/062 ,  H04L2463/101

    Abstract: A terminal for managing digital rights of a memory card inserted into the terminal and has a processor and a memory, the digital rights allowing the terminal to access digital contents. The terminal includes a processor configured to manage a digital rights and to exchange information with the memory card, the information including a terminal ID and a memory card ID; perform a mutual authentication procedure with the memory card; receive, from a contents provider, a trigger message which indicates to the terminal that a digital rights for the memory card is prepared in the contents provider; if a parameter included in the trigger message does not indicate the memory card, perform a procedure for obtaining a digital rights for the terminal; and if a parameter included in the trigger message indicates the memory card, perform a procedure for requesting a digital rights for the memory card.

    Abstract translation: 一种用于管理插入终端中的存储卡的数字版权的终端，具有处理器和存储器，该数字版权允许终端访问数字内容。 终端包括处理器，被配置为管理数字版权并与存储卡交换信息，该信息包括终端ID和存储卡ID; 与存储卡执行相互认证程序; 从内容提供者接收触发消息，向终端指示在内容提供商中准备存储卡的数字版权; 如果包括在触发消息中的参数不指示存储卡，则执行用于获得终端的数字版权的过程; 并且如果包括在触发消息中的参数指示存储卡，则执行请求存储卡的数字版权的过程。

    Method of manufacturing semiconductor device
    8.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08617991B2

    公开(公告)日：2013-12-31

    申请号：US13526960

    申请日：2012-06-19

    Applicant: Jung-Chan Lee ,  Yoo-Jung Lee ,  Ki-Hyung Ko ,  Dae-Young Kwak ,  Seung-Jae Lee ,  Jae-Sung Hur ,  Sang-Bom Kang ,  Cheol Kim ,  Bo-Un Yoon

    Inventor： Jung-Chan Lee ,  Yoo-Jung Lee ,  Ki-Hyung Ko ,  Dae-Young Kwak ,  Seung-Jae Lee ,  Jae-Sung Hur ,  Sang-Bom Kang ,  Cheol Kim ,  Bo-Un Yoon

    IPC: H01L21/44

    CPC classification number: H01L29/4983 ,  H01L21/76895 ,  H01L21/82345 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/78

    Abstract: A method of manufacturing a semiconductor device includes forming an interlayer dielectric film that has first and second trenches on first and second regions of a substrate, respectively, forming a first metal layer along a sidewall and a bottom surface of the first trench and along a top surface of the interlayer dielectric film in the first region, forming a second metal layer along a sidewall and a bottom surface of the second trench and along a top surface of the interlayer dielectric film in the second region, forming a first sacrificial layer pattern on the first metal layer such that the first sacrificial layer fills a portion of the first trench, forming a first electrode layer by etching the first metal layer and the second metal layer using the first sacrificial layer pattern, and removing the first sacrificial layer pattern.

    Abstract translation: 一种制造半导体器件的方法包括：在衬底的第一和第二区域上分别形成具有第一和第二沟槽的层间电介质膜，沿着第一沟槽的侧壁和底表面沿顶部形成第一金属层 在所述第一区域中的所述层间电介质膜的表面，沿着所述第二沟槽的侧壁和底表面沿着所述第二区域中的所述层间电介质膜的顶表面形成第二金属层，在所述第二区域中形成第一牺牲层图案 第一金属层，使得第一牺牲层填充第一沟槽的一部分，通过使用第一牺牲层图案蚀刻第一金属层和第二金属层形成第一电极层，以及去除第一牺牲层图案。

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