公开(公告)号：US06902981B2

公开(公告)日：2005-06-07

申请号：US10268315

申请日：2002-10-10

申请人： Chit Hwei Ng ,  Chaw Sing Ho

发明人： Chit Hwei Ng ,  Chaw Sing Ho

IPC分类号： H01L21/02 ,  H01L27/06 ,  H01L27/08 ,  H01L21/20 ,  H01L29/00

CPC分类号： H01L28/20 ,  H01L27/0682 ,  H01L27/0805 ,  H01L28/40

摘要： A structure and method of fabrication of a capacitor and other devices by providing a semiconductor structure and providing a top insulating layer and conductive features over the semiconductor structure; forming a first conductive layer over the top insulating layer; patterning the first conductive layer to form at least a capacitor bottom plate and a first portion of the first conductive layer; forming a capacitor dielectric layer over the top insulating layer and the capacitor bottom plate and the first portion of the first conductive layer; forming a second conductive layer over the capacitor dielectric layer; and patterning the second conductive layer to form at least a top plate over the bottom plate and a first section of the second conductive layer on the capacitor dielectric layer. The embodiment can further comprise conductive features in the top insulating layer that can underlie the bottom plate, the first portion or/and the first section. The first portion and the first section can form resistors, capacitors or other devices.

摘要翻译： 通过提供半导体结构并在半导体结构上提供顶部绝缘层和导电特征来制造电容器和其它器件的结构和方法; 在顶部绝缘层上形成第一导电层; 图案化第一导电层以形成至少电容器底板和第一导电层的第一部分; 在顶部绝缘层和电容器底板和第一导电层的第一部分上形成电容器电介质层; 在所述电容器介电层上形成第二导电层; 以及图案化所述第二导电层以在所述底板上形成至少顶板和在所述电容器电介质层上形成所述第二导电层的第一部分。 该实施例还可以包括顶层绝缘层中的导电特征，其可以位于底板，第一部分或/和第一部分的下面。 第一部分和第一部分可以形成电阻器，电容器或其他装置。

公开(公告)号：US06645810B2

公开(公告)日：2003-11-11

申请号：US10012292

申请日：2001-11-13

申请人： Chit Hwei Ng ,  Chaw Sing Ho

发明人： Chit Hwei Ng ,  Chaw Sing Ho

IPC分类号： H01L218242

CPC分类号： H01L23/5223 ,  H01L21/768 ,  H01L27/0805 ,  H01L28/55 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, the present invention recites forming a number of first openings in a first substrate. The present embodiment then recites forming a copper region within each first openings during a damascene process, wherein each copper region has a top surface. The present embodiment then disposes a dielectric layer proximate to the top surface of each of the first copper regions during the damascene process. After depositing a second substrate over the dielectric, a number of second openings in a second substrate are made. Next, a number of second copper regions are formed in the second openings, during the damascene process. The dielectric region is thus disposed between the first copper regions and the second copper regions. In so doing, the dielectric region forms a dielectric barrier between the first copper regions and the second copper regions such that a metal-insulator-metal (MIM) capacitor is formed during a damascene process.

摘要翻译： 在一个实施例中，本发明叙述在第一衬底中形成多个第一开口。 然后，本实施例在镶嵌工艺期间在每个第一开口内形成铜区，其中每个铜区具有顶表面。 然后，本实施例在镶嵌过程期间将电介质层布置成靠近每个第一铜区域的顶表面。 在电介质上沉积第二衬底之后，制成第二衬底中的多个第二开口。 接下来，在镶嵌工艺期间，在第二开口中形成多个第二铜区。 因此，电介质区域设置在第一铜区域和第二铜区域之间。 在这样做时，电介质区域在第一铜区域和第二铜区域之间形成电介质阻挡层，使得在镶嵌工艺期间形成金属 - 绝缘体 - 金属（MIM）电容器。

公开(公告)号：US06624040B1

公开(公告)日：2003-09-23

申请号：US10251350

申请日：2002-09-20

申请人： Chit Hwei Ng ,  Chaw Sing Ho ,  John E. Martin

发明人： Chit Hwei Ng ,  Chaw Sing Ho ,  John E. Martin

IPC分类号： H01L2176

CPC分类号： H01L23/5223 ,  H01L21/76811 ,  H01L27/0805 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper dual damascene process is described. A first dual damascene opening and a pair of second dual damascene openings are provided in a first dielectric layer overlying a substrate. The first and second dual damascene openings are filled with a first copper layer wherein the filled first dual damascene opening forms a logic interconnect and the filled pair of second dual damascene openings forms a pair of capacitor electrodes. The first dielectric layer is etched away between the pair of capacitor electrodes leaving a space between the pair of capacitor electrodes. The space between the pair of capacitor electrodes is filled with a high dielectric constant material to complete fabrication of a vertical MIM capacitor in the fabrication of an integrated circuit device. The fabrication of the capacitor can begin at any metal layer. The process of the invention can be extended to form a parallel capacitor, a series capacitor, stacked capacitors, and so on.

摘要翻译： 描述了使用集成铜双镶嵌工艺制造增加的电容金属 - 绝缘体 - 金属电容器的方法。 在衬底上的第一电介质层中设置有第一双镶嵌开口和一对第二双镶嵌开口。 第一和第二双镶嵌开口填充有第一铜层，其中填充的第一双镶嵌开口形成逻辑互连，并且填充的一对第二双镶嵌开口形成一对电容器电极。 在一对电容器电极之间蚀刻第一介电层，留下一对电容器电极之间的空间。 一对电容器电极之间的空间填充有高介电常数材料，以在集成电路器件的制造中完成纵向MIM电容器的制造。 电容器的制造可以从任何金属层开始。 本发明的方法可以扩展成并联电容器，串联电容器，堆叠电容器等。

公开(公告)号：US06528838B1

公开(公告)日：2003-03-04

申请号：US10012296

申请日：2001-11-13

申请人： Chit Hwei Ng ,  Chaw Sing Ho

发明人： Chit Hwei Ng ,  Chaw Sing Ho

IPC分类号： H01L27108

CPC分类号： H01L28/82 ,  H01L28/55

摘要： In one method embodiment, the present invention recites forming an opening in a substrate during a damascene process. The present embodiment then recites forming a dielectric region having two curvilinear surfaces opposite one another at least partially within the opening during the damascene process. The surfaces are curvilinear with respect to a horizontal cross-section. The present embodiment then recites forming a first copper region having a curvilinear surface proximate one of the surfaces of the dielectric region during the damascene process. The present embodiment then recites forming a second copper region having a curvilinear surface proximate a second surface of the dielectric region during the damascene process. In so doing, the dielectric region forms a dielectric barrier between the first copper region and the second copper region such that the vertical cylindrical MIM capacitor is formed.

摘要翻译： 在一个方法实施例中，本发明在镶嵌工艺期间背景在衬底中形成开口。 本实施例然后在镶嵌过程期间至少部分地在开口内形成具有彼此相对的两个曲线表面的电介质区域。 表面相对于水平横截面是曲线的。 然后，本实施例在镶嵌过程期间形成具有靠近电介质区域的一个表面的曲线表面的第一铜区域。 然后，本实施例在镶嵌过程期间叙述形成具有靠近电介质区域的第二表面的曲线表面的第二铜区域。 这样，电介质区域在第一铜区域和第二铜区域之间形成电介质阻挡层，从而形成垂直圆柱形MIM电容器。

公开(公告)号：US06730573B1

公开(公告)日：2004-05-04

申请号：US10286257

申请日：2002-11-01

申请人： Chit Hwei Ng ,  Chaw Sing Ho ,  Lup San Leong ,  Shao Kai ,  Raymond Jacob Joy ,  Sanford Chu ,  Sajan Marokkey Raphael

发明人： Chit Hwei Ng ,  Chaw Sing Ho ,  Lup San Leong ,  Shao Kai ,  Raymond Jacob Joy ,  Sanford Chu ,  Sajan Marokkey Raphael

IPC分类号： H01L2120

CPC分类号： H01L28/24 ,  H01L21/76838 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5252 ,  H01L23/5329 ,  H01L27/0682 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved process for fabricating simultaneously high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, has been developed using single or dual damascene processing. The key advantage is the use of only one additional mask reticle to form both MIM capacitor and resistor, simultaneously. Several current obstacles that exist in BEOL, back end of line, are overcome, namely: (a) the use of two or more photo-masks to make

摘要翻译： 已经开发了使用单镶嵌或双镶嵌加工制造同时高容量，小于0.13微米的金属 - 绝缘体 - 金属电容器，金属电阻器和金属互连的改进方法。 关键的优点是同时使用一个额外的掩模掩模版同时形成MIM电容和电阻。 克服了BEOL后端存在的几个当前的障碍，即：（a）使用两个或更多个光掩膜使<0.13μm的MIM电容器，（b）凹凸的铜表面，当电介质直接沉积时 （c）当在底部MIM板层上尝试蚀刻停止时，（c）蚀刻期间的颗粒产生问题，最后，（d）在需要大的铜MIM板时发生CMP期间的凹陷，随后的电容匹配问题。 该集成方法克服了上述障碍，同时使用镶嵌处理形成MIM电容器，金属电阻器和金属互连。 此外，本文所述的形成MIM电容器的方法也可用于在现场可编程门阵列FPGA中形成反熔丝器件。

公开(公告)号：US06709918B1

公开(公告)日：2004-03-23

申请号：US10307674

申请日：2002-12-02

申请人： Chit Hwei Ng ,  Jian Xun Li ,  Kok Wai Chew ,  Tjin Tjin Tjoa ,  Chaw Sing Ho ,  Shao Fu Sanford Chu

发明人： Chit Hwei Ng ,  Jian Xun Li ,  Kok Wai Chew ,  Tjin Tjin Tjoa ,  Chaw Sing Ho ,  Shao Fu Sanford Chu

IPC分类号： H01L218242

CPC分类号： H01L28/20 ,  H01L23/5223 ,  H01L23/5228 ,  H01L28/40 ,  H01L2924/0002 ,  Y10S438/959 ,  H01L2924/00

摘要： A method for making concurrently metal-insulator-metal (MIM) capacitors and a metal resistors in a Cu damascene back-end-of-line process is achieved. The method forms a Cu capacitor bottom metal plate using a dual-damascene process. A Si3N4 or SiC is deposited to form a capacitor dielectric layer on the Cu bottom plate. A metal layer having an upper etch-stop layer is deposited and patterned to form concurrently capacitor top plates and metal resistors. The patterning is terminated in the capacitor dielectric layer to prevent Cu particle contamination. An insulating layer is deposited and via holes are etched to the capacitor top plates and the metal resistors using the upper etch-stop layer to prevent overetching and damage. The method provides a MIM capacitor using only one additional photoresist mask while improving process yield.

摘要翻译： 实现了一种在金铜绝缘体金属（MIM）电容器和金属电阻器Cu铜镶嵌后端工艺中的制造方法。 该方法使用双镶嵌工艺形成Cu电容器底部金属板。 沉积Si 3 N 4或SiC以在Cu底板上形成电容器电介质层。 具有上蚀刻停止层的金属层被沉积​​并图案化以形成电容器顶板和金属电阻器。 图案化终止在电容器电介质层中以防止Cu颗粒污染。 沉积绝缘层，并且使用上蚀刻停止层将电容器顶板和金属电阻器的通孔蚀刻以防止过蚀刻和损坏。 该方法提供了仅使用一种附加光致抗蚀剂掩模的MIM电容器，同时提高了工艺产量。

公开(公告)号：US06548367B1

公开(公告)日：2003-04-15

申请号：US10120105

申请日：2002-04-09

申请人： Chit Hwei Ng ,  Chaw Sing Ho

发明人： Chit Hwei Ng ,  Chaw Sing Ho

IPC分类号： H01L2120

CPC分类号： H01L28/82 ,  H01L28/55

摘要： In one method embodiment, the present invention recites forming an opening in a substrate during a damascene process. The present embodiment then recites forming a dielectric region having two curvilinear surfaces opposite one another at least partially within the opening during the damascene process. The surfaces are curvilinear with respect to a horizontal cross-section. The present embodiment then recites forming a first copper region having a curvilinear surface proximate one of the surfaces of the dielectric region during the damascene process. The present embodiment then recites forming a second copper region having a curvilinear surface proximate a second surface of the dielectric region during the damascene process. In so doing, the dielectric region forms a dielectric barrier between the first copper region and the second copper region such that the vertical cylindrical MIM capacitor is formed.

摘要翻译： 在一个方法实施例中，本发明在镶嵌工艺期间背景在衬底中形成开口。 本实施例然后在镶嵌过程期间至少部分地在开口内形成具有彼此相对的两个曲线表面的电介质区域。 表面相对于水平横截面是曲线的。 然后，本实施例在镶嵌过程期间形成具有靠近电介质区域的一个表面的曲线表面的第一铜区域。 然后，本实施例在镶嵌过程期间叙述形成具有靠近电介质区域的第二表面的曲线表面的第二铜区域。 这样，电介质区域在第一铜区域和第二铜区域之间形成电介质阻挡层，从而形成垂直圆柱形MIM电容器。

公开(公告)号：US06410376B1

公开(公告)日：2002-06-25

申请号：US09797555

申请日：2001-03-02

申请人： Chit Hwei Ng ,  Chaw Sing Ho

发明人： Chit Hwei Ng ,  Chaw Sing Ho

IPC分类号： H01L218238

CPC分类号： H01L21/823878 ,  H01L21/823842

摘要： A new method for forming a dual-metal gate CMOS transistors is described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A nitride layer is deposited overlying a gate dielectric layer and patterned to form a first dummy gate in each of the active areas. First ions are implanted to form source/drain regions in each of the active areas not covered by the first dummy gates. The first dummy gates are isotropically etched to form second dummy gates thinner than the first dummy gates. Second ions are implanted to form lightly doped source/drain regions in each of the active areas not covered by the second dummy gates. Dielectric spacers are formed on sidewalls of the second dummy gates and the source/drain regions are silicided. A dielectric layer is deposited and planarized to the second dummy gates. Thereafter, the second dummy gates are removed, leaving gate openings in the dielectric layer. A mask is formed over the PMOS active area. A first metal layer is deposited in the gate opening in the NMOS active area and planarized to the mask. The mask is removed. A second metal layer is deposited in the gate opening in the PMOS active area. The first and second metal layers are polished away to the dielectric layer thereby completing formation of dual-metal gate CMOS transistors in the fabrication of an integrated circuit.

摘要翻译： 描述了形成双金属栅极CMOS晶体管的新方法。 半导体衬底的NMOS和PMOS有源区由隔离区隔开。 沉积覆盖在栅极电介质层上的氮化物层并且被图案化以在每个有源区域中形成第一伪栅极。 植入第一离子以在未被第一伪栅极覆盖的每个有源区域中形成源极/漏极区域。 第一伪栅极被各向同性地蚀刻以形成比第一伪栅极薄的第二虚拟栅极。 注入第二离子以在未被第二伪栅极覆盖的每个有源区域中形成轻掺杂的源极/漏极区域。 电介质隔板形成在第二伪栅极的侧壁上，并且源极/漏极区域被硅化。 介电层沉积并平面化到第二虚拟栅极。 此后，去除第二伪栅极，在电介质层中留下栅极开口。 在PMOS有源区上形成掩模。 第一金属层沉积在NMOS有源区中的栅极开口中并且平坦化到掩模。 去除面具。 第二金属层沉积在PMOS有源区的栅极开口中。 将第一和第二金属层抛光到介电层，从而在集成电路的制造中完成双金属栅极CMOS晶体管的形成。

公开(公告)号：US20100295153A1

公开(公告)日：2010-11-25

申请号：US12471007

申请日：2009-05-22

申请人： Shao-fu Sanford Chu ,  Shaoqing Zhang ,  Johnny Kok Wai Chew ,  Chit Hwei Ng

发明人： Shao-fu Sanford Chu ,  Shaoqing Zhang ,  Johnny Kok Wai Chew ,  Chit Hwei Ng

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L23/5223 ,  H01L27/0207 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers with the second group of metal layers to form a capacitor.

摘要翻译： 一种制造集成电路系统的方法包括：提供包括前端电路的基板; 利用第一设计规则在所述衬底上形成包括第一手指和第二手指的第一组金属层，所述第一组金属层形成为没有手指通孔; 利用大于第一设计规则的第二设计规则，在第一组金属层上形成包括第一手指，第二手指和手指通孔的第二组金属层; 并且将所述第一组金属层与所述第二组金属层互连以形成电容器。

公开(公告)号：US06903013B2

公开(公告)日：2005-06-07

申请号：US10439923

申请日：2003-05-16

申请人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Yong Ju ,  Jia Zhen Zheng

发明人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Yong Ju ,  Jia Zhen Zheng

IPC分类号： H01L21/285 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76873 ,  H01L23/5227 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved method to deposit, by atomic layer deposition, ALD, a copper barrier and seed layer for electroless copper plating, filling trench and channel or tunnel openings in a damascene process, for the fabrication of interconnects and inductors, has been developed. A process flow outlining the method of the present invention is as follows: (1) formation of trenches and channels, (2) atomic layer deposition of copper barrier and seed, (3) electroless deposition of copper, (4) chemical mechanical polishing back of excess copper, and (5) barrier deposition, SiN, forming copper interconnects and inductors.

摘要翻译： 已经开发了一种改进的方法，通过原子层沉积，ALD，用于化学镀铜的铜屏障和种子层，在镶嵌工艺中的填充沟槽和沟道或隧道开口，用于制造互连和电感器。 概述本发明方法的工艺流程如下：（1）形成沟槽和通道，（2）铜屏障和晶种的原子层沉积，（3）铜的无电沉积，（4）化学机械抛光 的过量铜，和（5）阻挡层沉积，SiN，形成铜互连和电感器。