公开(公告)号：US09078301B2

公开(公告)日：2015-07-07

申请号：US13414699

申请日：2012-03-07

申请人： Po-Ching Li ,  Chao-Chih Hsiao

发明人： Po-Ching Li ,  Chao-Chih Hsiao

IPC分类号： H05B37/02 ,  G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3648 ,  G09G2320/0219 ,  H05B37/02

摘要： Output stage circuit is added to the gate driving circuit of the LCD. The output stage circuit moderates the falling slope of the gate driving signal so as to reduce the feed-through phenomenon. The output stage circuit includes a discharge circuit which discharges the voltage of the gate driving signal with programmable speeds. The discharge circuit has a plurality of discharge units which are turned on sequentially and designed with different driving abilities. At beginning of falling of the gate driving signal, the discharge circuit discharges the gate driving signal with lower driving ability so that the gate driving signal falls with a lower speed. As time passes, the falling speed of the gate driving signal increases by the increasing of the driving ability of the discharge circuit. The entire falling period of the gate driving signal is prolonged by the output stage circuit and the feed-through phenomenon is eased.

摘要翻译： 输出级电路被添加到LCD的栅极驱动电路。 输出级电路调节栅极驱动信号的下降斜率，以减少馈通现象。 输出级电路包括以可编程速度放电门驱动信号的电压的放电电路。 放电电路具有顺序地开启并且设计成具有不同驱动能力的多个放电单元。 在栅极驱动信号的下降开始时，放电电路以较低的驱动能力放电栅极驱动信号，使得栅极驱动信号以较低的速度下降。 随着时间的推移，栅极驱动信号的下降速度随着放电电路的驱动能力的增加而增加。 栅极驱动信号的整个下降周期被输出级电路延长，并且馈通现象得到缓解。

公开(公告)号：US20120007235A1

公开(公告)日：2012-01-12

申请号：US13106879

申请日：2011-05-13

申请人： Chao-Chih Hsiao ,  Po-Ching Li

发明人： Chao-Chih Hsiao ,  Po-Ching Li

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L23/4985 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17517 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/00

摘要： A chip fanning out method is disclosed. The chip fanning out method includes mounting a chip on a film, forming a plurality of outer lead bonds spatially arranged in a bump correspondence order on the film, forming a plurality of bumps spatially arranged in a bump arrangement order on the chip, and forming a plurality of wires to connect the plurality of outer lead bonds to the plurality of bumps according to the bump correspondence order, wherein the bump correspondence order is different from the bump arrangement order.

摘要翻译： 公开了一种芯片扇出方法。 芯片扇出方法包括将芯片安装在薄膜上，在薄膜上形成以凸起对应的顺序空间上排列的多个外部引线键，形成以芯片上的凸块布置顺序空间排列的多个凸起，并形成 多个导线，根据凸点对应次序将多个外部引线接合部连接到多个凸起部，其中凸起对应次序不同于凸块布置次序。

公开(公告)号：US20100033225A1

公开(公告)日：2010-02-11

申请号：US12264187

申请日：2008-11-03

申请人： Chao-Chih Hsiao ,  Yen-Po Chen

发明人： Chao-Chih Hsiao ,  Yen-Po Chen

IPC分类号： H03L5/00

CPC分类号： H01L27/1203 ,  H01L21/82385 ,  H01L27/0207 ,  H01L27/0922

摘要： A gate driving circuit includes a first output buffer unit region, a level shifter region and a low voltage circuit region. The first output buffer unit region is formed on a plane and is utilized for setting a first output buffer unit. The level shifter region is formed on the plane for setting a level shifter, and includes a vertical region and a horizontal region connected to the vertical region. The vertical region and the first output buffer unit region are aligned in a horizontal direction of the plane. The horizontal region is beneath the vertical region and the first output buffer unit region. The low voltage circuit region is formed on the plane for setting a low voltage circuit, and is beneath the horizontal region. The low voltage circuit region and the horizontal region are aligned in a vertical direction of the plane.

摘要翻译： 栅极驱动电路包括第一输出缓冲器单元区域，电平移位器区域和低电压电路区域。 第一输出缓冲单元区域形成在平面上，并用于设置第一输出缓冲单元。 电平移位器区域形成在用于设置电平移位器的平面上，并且包括连接到垂直区域的垂直区域和水平区域。 垂直区域和第一输出缓冲单元区域在平面的水平方向上对准。 水平区域在垂直区域和第一输出缓冲单元区域之下。 低电压电路区域形成在用于设置低电压电路的平面上，并且在水平区域之下。 低电压电路区域和水平区域在平面的垂直方向上排列。

公开(公告)号：US20090243656A1

公开(公告)日：2009-10-01

申请号：US12168160

申请日：2008-07-07

申请人： Chao-Chih Hsiao

发明人： Chao-Chih Hsiao

IPC分类号： H03K19/094

CPC分类号： H03K19/0013 ,  H03K5/1515

摘要： In order to reduce production cost, an output buffer for an electronic device includes a first logic unit, a second logic unit, a first transistor, a second transistor and a control unit. The first logic unit and the second unit are both coupled to an input terminal and conductions of the first logic unit and the second unit are controlled by an input signal from the input terminal. The control unit is coupled to the first logic unit, the second logic unit, the first transistor and the second transistor, for controlling the first transistor and the second transistor to conduct at different times for implementing the non-overlapping function.

摘要翻译： 为了降低生产成本，用于电子设备的输出缓冲器包括第一逻辑单元，第二逻辑单元，第一晶体管，第二晶体管和控制单元。 第一逻辑单元和第二单元都耦合到输入端子，并且通过来自输入端子的输入信号来控制第一逻辑单元和第二单元的导通。 控制单元耦合到第一逻辑单元，第二逻辑单元，第一晶体管和第二晶体管，用于控制第一晶体管和第二晶体管在不同时间导通以实现非重叠功能。

公开(公告)号：US20110102416A1

公开(公告)日：2011-05-05

申请号：US12828301

申请日：2010-07-01

申请人： Ching-Ho Hung ,  Chao-Chih Hsiao ,  Yen-Po Chen ,  Bor-Chun Wu

发明人： Ching-Ho Hung ,  Chao-Chih Hsiao ,  Yen-Po Chen ,  Bor-Chun Wu

IPC分类号： G06F3/038

CPC分类号： G09G3/3677

摘要： A gate driving circuit for an LCD device includes a shift register module for generating a plurality of scan signals corresponding to a plurality of channels according to a start signal and a clock signal, a plurality of logic circuits each corresponding to a channel of the plurality of channels, for outputting a driving signal to the channel according to a scan signal of the plurality of scan signals and a shutdown indication signal, and a plurality of shaping and delay units each coupled between two neighboring channels for outputting the shutdown indication signal to another channel after shaping and delaying the shutdown indication signal of a previous stage.

摘要翻译： 一种用于LCD装置的栅极驱动电路包括：移位寄存器模块，用于根据起始信号和时钟信号产生对应于多个信道的多个扫描信号，多个逻辑电路各自对应于多个信道 通道，用于根据多个扫描信号的扫描信号和关闭指示信号向通道输出驱动信号，以及多个整形和延迟单元，每个均衡和延迟单元都耦合在两个相邻通道之间，用于将关闭指示信号输出到另一个通道 在对前一阶段的关闭指示信号进行整形和延迟之后。

公开(公告)号：US20100272228A1

公开(公告)日：2010-10-28

申请号：US12504665

申请日：2009-07-17

申请人： Chao-Chih Hsiao ,  Yen-Po Chen

发明人： Chao-Chih Hsiao ,  Yen-Po Chen

IPC分类号： G11C19/00

CPC分类号： G11C19/184

摘要： A shift register apparatus is provided. Each of shift registers within the shift register apparatus of the present invention is only constituted by a few of active and passive elements without using conventional digital logic elements, and even the passive element are not required at some conditions. Therefore, the layout area occupied/consumed by each of the shift registers of the present invention is relatively smaller than that of the conventional shift register constituted by a CMOS D-flip-flop, and thus a fabrication cost can be reduced.

摘要翻译： 提供一种移位寄存器装置。 本发明的移位寄存器装置中的每个移位寄存器仅由少数有源和无源元件构成，而不使用传统的数字逻辑元件，甚至在某些情况下也不需要无源元件。 因此，本发明的每个移位寄存器占用/消耗的布局面积相对于由CMOS D触发器构成的传统移位寄存器的布局面积相对较小，因此可以降低制造成本。

公开(公告)号：US07719306B2

公开(公告)日：2010-05-18

申请号：US12168160

申请日：2008-07-07

申请人： Chao-Chih Hsiao

发明人： Chao-Chih Hsiao

IPC分类号： H03K3/00

CPC分类号： H03K19/0013 ,  H03K5/1515

摘要： In order to reduce production cost, an output buffer for an electronic device includes a first logic unit, a second logic unit, a first transistor, a second transistor and a control unit. The first logic unit and the second unit are both coupled to an input terminal and conductions of the first logic unit and the second unit are controlled by an input signal from the input terminal. The control unit is coupled to the first logic unit, the second logic unit, the first transistor and the second transistor, for controlling the first transistor and the second transistor to conduct at different times for implementing the non-overlapping function.

摘要翻译： 为了降低生产成本，用于电子设备的输出缓冲器包括第一逻辑单元，第二逻辑单元，第一晶体管，第二晶体管和控制单元。 第一逻辑单元和第二单元都耦合到输入端子，并且通过来自输入端子的输入信号来控制第一逻辑单元和第二单元的导通。 控制单元耦合到第一逻辑单元，第二逻辑单元，第一晶体管和第二晶体管，用于控制第一晶体管和第二晶体管在不同时间导通以实现非重叠功能。

公开(公告)号：US20130234626A1

公开(公告)日：2013-09-12

申请号：US13414699

申请日：2012-03-07

申请人： Po-Ching Li ,  Chao-Chih Hsiao

发明人： Po-Ching Li ,  Chao-Chih Hsiao

IPC分类号： H05B37/02

CPC分类号： G09G3/3677 ,  G09G3/3648 ,  G09G2320/0219 ,  H05B37/02

摘要： Output stage circuit is added to the gate driving circuit of the LCD. The output stage circuit moderates the falling slope of the gate driving signal so as to reduce the feed-through phenomenon. The output stage circuit includes a discharge circuit which discharges the voltage of the gate driving signal with programmable speeds. The discharge circuit has a plurality of discharge units which are turned on sequentially and designed with different driving abilities. At beginning of falling of the gate driving signal, the discharge circuit discharges the gate driving signal with lower driving ability so that the gate driving signal falls with a lower speed. As time passes, the falling speed of the gate driving signal increases by the increasing of the driving ability of the discharge circuit. The entire falling period of the gate driving signal is prolonged by the output stage circuit and the feed-through phenomenon is eased.

摘要翻译： 输出级电路被添加到LCD的栅极驱动电路。 输出级电路调节栅极驱动信号的下降斜率，以减少馈通现象。 输出级电路包括以可编程速度放电门驱动信号的电压的放电电路。 放电电路具有顺序地开启并且设计成具有不同驱动能力的多个放电单元。 在栅极驱动信号的下降开始时，放电电路以较低的驱动能力放电栅极驱动信号，使得栅极驱动信号以较低的速度下降。 随着时间的推移，栅极驱动信号的下降速度随着放电电路的驱动能力的增加而增加。 栅极驱动信号的整个下降周期被输出级电路延长，并且馈通现象得到缓解。

公开(公告)号：US20100103163A1

公开(公告)日：2010-04-29

申请号：US12369743

申请日：2009-02-12

申请人： Chao-Chih Hsiao

发明人： Chao-Chih Hsiao

IPC分类号： G09G5/00

CPC分类号： G09G3/3677 ,  G09G3/3696 ,  G09G2310/0289

摘要： A driver apparatus applied on a display is disclosed. The driver apparatus includes a voltage converter, an input level shift circuit, at least one input logic circuit, and at least one output level shifter. The voltage converter receives a first voltage, a ground voltage, and a second voltage, and generates an internal voltage according to the first voltage, the ground voltage, and the second voltage. The input level shift circuit receives an input signal, and generates a level shift input signal transiting between the first voltage and the second voltage according to the input signal. The input logic circuit receives the internal voltage, and generates an internal output signal transiting between the internal voltage and the second voltage according to the level shift input signal. The output level shifter generates a driving signal transiting between a third voltage and the second voltage according to the internal output signal.

摘要翻译： 公开了一种应用在显示器上的驱动装置。 驱动器装置包括电压转换器，输入电平移位电路，至少一个输入逻辑电路和至少一个输出电平转换器。 电压转换器接收第一电压，接地电压和第二电压，并且根据第一电压，接地电压和第二电压产生内部电压。 输入电平移位电路接收输入信号，并根据输入信号产生在第一电压和第二电压之间转移的电平移位输入信号。 输入逻辑电路接收内部电压，并根据电平移位输入信号产生内部电压和第二电压之间的内部输出信号。 输出电平转换器根据内部输出信号产生在第三电压和第二电压之间的驱动信号。

公开(公告)号：US07292107B2

公开(公告)日：2007-11-06

申请号：US11163356

申请日：2005-10-17

申请人： Chao-Chih Hsiao ,  Min-Chieh Hsu ,  Ping-Hsun Hsieh

发明人： Chao-Chih Hsiao ,  Min-Chieh Hsu ,  Ping-Hsun Hsieh

IPC分类号： H03L7/00 ,  H03C3/00

CPC分类号： H03C3/0925 ,  H03C3/0941 ,  H03C3/0966 ,  H03C3/0975

摘要： A modulation method and a modulation apparatus in a phase-locked loop (PLL) provided. The modulation apparatus comprises a modulator, a crystal oscillator, a controllable R-divisor frequency divider, a controllable N-divisor frequency divider and a voltage-controlled oscillator (VCO). The crystal oscillator generates a fixed frequency oscillating signal. The controllable R-divisor frequency divider receives the oscillating signal from the crystal oscillator and divides the frequency by R. The VCO generates a frequency signal based on a voltage-controlled signal provided by the PLL and feedbacks the frequency signal to the controllable N-divisor frequency divider. The controller N-divisor frequency divider receives a feedback frequency from the VCO and divides the frequency by N. A PLL unit used to compare a frequency provided by the crystal oscillator and passed through the controllable R-divisor frequency divider, with a frequency provided by the VCO and passed through the controllable N-divisor frequency divider, for performing a phase-locked operation.

摘要翻译： 提供了锁相环（PLL）中的调制方法和调制装置。 调制装置包括调制器，晶体振荡器，可控R因数分频器，可控N因数分频器和压控振荡器（VCO）。 晶体振荡器产生固定频率振荡信号。 可控R因数分频器接收来自晶体振荡器的振荡信号，并将频率除以R. VCO产生基于由PLL提供的电压控制信号的频率信号，并将频率信号反馈到可控N因数 分频器 控制器N除数分频器从VCO接收反馈频率并将频率除以N.用于比较由晶体振荡器提供的频率并通过可控R因数分频器的频率的PLL单元，频率由 VCO并通过可控N因数分频器，用于执行锁相操作。