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公开(公告)号：US11468951B2
公开(公告)日：2022-10-11
申请号：US17458186
申请日：2021-08-26
发明人： Hong Nie , Jingwei Chen
IPC分类号： G11C16/04 , G11C16/10 , G11C16/14 , H01L27/11521 , H01L29/788
摘要： The present disclosure relates to a method for programming flash memory, which includes: providing a flash memory structure having a floating gate, and floating a source of the flash memory structure; separately applying voltages to a drain and a substrate, to form an electric field, and generating electron-hole pairs, to generate primary electrons, where the voltage applied to the substrate is less than the voltage applied to the drain; accelerating holes downward under the action of the electric field to collide with the substrate in the flash memory structure within a preset time, to generate secondary electrons; and separately applying voltages to a gate and the substrate, where the voltage applied to the substrate is less than the voltage applied to the gate, and enabling the secondary electrons to generate tertiary electrons to inject the tertiary electrons into the floating gate, to complete a programming operation.
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公开(公告)号：US11355196B2
公开(公告)日：2022-06-07
申请号：US17380720
申请日：2021-07-20
发明人： Hong Nie , Jingwei Chen
摘要： The present disclosure relates to a method for programming a NAND flash memory, which includes: providing a NAND flash memory array, and initializing a to-be-programmed memory cell; applying a drain voltage to the drain of the to-be-programmed memory cell, and floating the source of the to-be-programmed memory cell; and applying a programming voltage to the gate of the to-be-programmed memory cell, and discharging the voltage at each end of the to-be-programmed memory cell after maintaining the voltage for a first time period, to complete programming; a difference between the voltage applied to the drain and the voltage applied to the substrate of the to-be-programmed memory cell being not less than 4 V, the first time period being not longer than 100 μs, and the programming voltage being not higher than 10 V.
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公开(公告)号：US11386962B2
公开(公告)日：2022-07-12
申请号：US17486908
申请日：2021-09-27
发明人： Hong Nie , Jingwei Chen
摘要： The present disclosure relates to a method for programming a 3D NAND flash memory, which includes: S1) providing a 3D flash memory array, and eliminating residual charges; S2) strobing a bit line where an upper sub-storage module is located; S3) applying a drain voltage to the drain of a to-be-programmed memory cell, and floating a source thereof; S4) applying a programming voltage to the gate of the to-be-programmed memory cell, to complete programming; and S5) after completing the programming of the upper sub-storage module, and when the upper sub-storage module keeps a programmed state, strobing a bit line where a lower sub-storage module is located, and repeating operation S3) and operation S4) to achieve programming of the lower sub-storage module. In the method for programming a 3D NAND flash memory according to the present disclosure, programming is completed based on tertiary electron collision.
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公开(公告)号：US11348645B1
公开(公告)日：2022-05-31
申请号：US17465272
申请日：2021-09-02
发明人： Hong Nie , Jingwei Chen
摘要： A method for programming a B4 flash memory includes: floating a source of a P-channel flash memory device; separately applying voltages to a gate, a drain, and a bulk of the P-channel flash memory device, and injecting holes into the bulk, so that electrons are gathered in the drain to form primary electrons; separately applying voltages to the drain and the bulk, so that an electric field is formed between the drain and the bulk, where the holes accelerate downward under the action of the electric field and impact the bulk in the P-channel flash memory device to generate secondary electrons; and separately applying voltages to the gate and the bulk of the P-channel flash memory device, so that the secondary electrons form tertiary electrons under the action of the electric field in a vertical direction, where the tertiary electrons are superposed with the primary electrons to be injected into a floating gate.
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公开(公告)号：US11875857B2
公开(公告)日：2024-01-16
申请号：US17576985
申请日：2022-01-16
发明人： Hong Nie , Jingwei Chen
IPC分类号： G11C16/04 , G11C16/14 , H10B41/30 , H01L29/788 , G11C16/10
CPC分类号： G11C16/14 , G11C16/0408 , H10B41/30 , G11C16/0483 , G11C16/10 , H01L29/7881
摘要： A method for programming a memory. The method includes providing a memory structure with a floating gate, and grounding a source of the memory structure; applying voltages to a drain and a bulk, forming an electric field, generating electron-hole pairs, and generating primary electrons, wherein the voltage applied to the bulk is lower than the voltage applied to the drain; making holes accelerate downward under the action of the electric field and collide with the bulk in the memory structure within a predetermined time to generate secondary electrons; applying voltages to a gate and the bulk respectively, where the voltage applied to the bulk is lower than the voltage applied to the gate, to enable the secondary electrons to generate tertiary electrons under the action of an electric field in a vertical direction, and the tertiary electrons are injected into the floating gate to complete a programming operation.
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公开(公告)号：US11862259B2
公开(公告)日：2024-01-02
申请号：US17899167
申请日：2022-08-30
CPC分类号： G11C16/3477
摘要： An electronic device, and an over-erase detection and elimination method for memory cells are provided; the method includes: performing an erase operation on a specified area; selecting all the memory cells in the selected area one by one; measuring a threshold voltage of a selected memory cell for over-erase detection to see if it is less than a normal erase threshold voltage; if not, selecting the next memory cell for over-erase detection, and if yes, then performing a soft-write operation on the selected memory cell; after the soft-write operation, performing over-erase detection again to see whether the threshold voltage of the selected memory cell is within a normal threshold range; and if not, performing a soft-write operation again, and if yes, the next memory cell is selected for over-erase detection, until the threshold voltages of all the memory cells selected for erasure are within the normal threshold range.
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公开(公告)号：US11176298B1
公开(公告)日：2021-11-16
申请号：US17221265
申请日：2021-04-02
IPC分类号： G06F30/30 , G06F30/3308 , G06F30/3323 , G06F30/367 , G06F30/33
摘要： The present disclosure provides a method for modeling, including: S1): designing a test key having a source, a drain, and a gate, and testing the test key to obtain test data; S2): extracting a model parameter according to the test data; S3): verifying reasonableness of a physical characteristic of the model parameter based on a relationship between a source-drain voltage and a drain current, if the reasonableness passes the verification, a model file is established and the method proceeds to S4), if the reasonableness fails the verification, the method returns to S2) to adjust the model parameter, until the reasonableness passes the verification; S4): performing quality assurance on the model file, if the model file passes the quality assurance, the modeling is completed, if the model file fails the quality assurance, the method returns to S2) to adjust the model parameter until the model file passes the quality assurance.
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公开(公告)号：US11587625B1
公开(公告)日：2023-02-21
申请号：US17878489
申请日：2022-08-01
摘要： A sensitive amplifier and a storage device are provided, and the sensitive amplifier includes: a voltage clamp circuit which provides a stable reading voltage for the storage unit; a power switch circuit which cuts off power supply for the voltage clamp circuit when the voltage clamp circuit is not operating; a discharge circuit which discharges the voltage clamp circuit before the voltage clamp circuit operates; a pre-charge circuit which pre-charges the voltage clamp circuit when the voltage clamp circuit starts operating; and a current comparison circuit which is connected to an output of the voltage clamp circuit, compares the reading current with a reference current, and outputs a comparison result.
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公开(公告)号：US11410738B1
公开(公告)日：2022-08-09
申请号：US17566643
申请日：2021-12-30
IPC分类号： G11C5/00 , G11C16/34 , G11C16/14 , G11C16/10 , H03K19/0948 , G11C16/08 , G11C16/30 , G11C16/04 , G11C16/26
摘要： A word line decoding circuit and memory comprises a first address decoding module to obtain word line logic signals; a word line pre-coding module to obtain word line pre-coding signals and first switch signals; a second address decoding module to obtain first and second selection signals; a third address decoding module to obtain third selection signals; a first level conversion module which performs level conversion on the first selection signals to obtain first and second control signals; a second level conversion module which performs level conversion on the second selection signals to get third and fourth control signals; a third level conversion module which performs level conversion on the third selection signals to obtain fifth control signals; a word line toggle switch signal generation module which generates second switch signals based on each control signal; and a word line toggle module to generate word line signals.
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