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公开(公告)号：US20230055868A1
公开(公告)日：2023-02-23
申请号：US17599459
申请日：2021-06-08
发明人： Tao CHEN
IPC分类号： H01L21/02 , H01L27/108
摘要： The embodiments of the present disclosure propose a method for resolving a defect of surface structures of trenches and a method for preparing a semiconductor structure. The method for resolving a defect of surface structures of trenches includes: cleaning the trenches on a base with a cleaning liquid after the trenches are formed on the base, where the cleaning liquid is water.
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公开(公告)号：US20220352177A1
公开(公告)日：2022-11-03
申请号：US17600828
申请日：2021-06-30
发明人： Junchao ZHANG , Tao CHEN
IPC分类号： H01L27/108 , H01L29/66 , H01L21/302
摘要： A manufacturing method for memory includes: providing a substrate, and forming a first isolation layer and discrete bit lines on the substrate; removing part of the first isolation layer by a thickness to form discrete first trenches; forming word lines filling the first trenches, wherein the word lines each has a first side wall and a second side wall opposite to each other; forming discrete through holes each being between adjacent word lines; forming a first dielectric layer on surface of exposed first side wall, and forming a second dielectric layer on surface of exposed second side wall; and forming an active layer filling the through holes.
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3.发明申请公开(公告)号：US20220310618A1
公开(公告)日：2022-09-29
申请号：US17430410
申请日：2021-03-01
发明人： Tao CHEN , Cheng Yeh HSU , WenHao Hsieh
IPC分类号： H01L27/108
摘要： The present application relates to the technical field of semiconductor manufacturing, in particular to a method for forming a film layer with uniform thickness distribution and a semiconductor structure. The method for forming a film layer with uniform thickness distribution comprises: providing a substrate, a non-flat surface for forming a film layer being provided in the substrate; forming a first sub-layer on the non-flat surface at a first temperature by an in-situ steam generation process; and, forming a second sub-layer on a surface of the first sub-layer at a second temperature by an in-situ steam generation process, the film layer at least comprising the first sub-layer and the second sub-layer, the second temperature being higher than the first temperature.
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公开(公告)号：US20220059695A1
公开(公告)日：2022-02-24
申请号：US17404114
申请日：2021-08-17
IPC分类号： H01L29/78 , H01L27/088 , H01L29/423 , H01L29/10 , H01L21/265 , H01L21/8234
摘要： The application provides a method for manufacturing a semiconductor device. The method includes the following operations. A semiconductor substrate is provided, a plurality of separate trenches being formed in the semiconductor substrate. Plasma injection is performed to form a barrier layer between adjacent trenches A respective gate structure is formed in each of the plurality of trenches. A plurality of channel regions are formed in the semiconductor substrate, each of the plurality of trenches corresponding to a respective one of the plurality of channel regions. A source/drain region is formed between each of the plurality of trenches and the barrier layer, the source/drain region being electrically connected to the respective one of the plurality of channel regions, and a conductive type of the barrier layer is opposite to a conductive type of the source/drain region.
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公开(公告)号：US20220285352A1
公开(公告)日：2022-09-08
申请号：US17447198
申请日：2021-09-08
发明人： Tao CHEN
IPC分类号： H01L27/108
摘要： A memory includes a substrate. An isolation layer is disposed on the substrate. The plurality of active regions arranged in an array are disposed in the isolation layer. A plurality of word lines are formed in the plurality of active regions and the isolation layer. Each word line includes gates disposed in the active regions and word line structures disposed in the isolation layer. The each word line is constituted by successive connection of the plurality of gates and the plurality of word line structures arranged at intervals. The plurality of gates included in the each word line are disposed in two correspondingly adjacent columns of active regions, and any two adjacent gates in the each word line are disposed in two correspondingly adjacent rows of active regions.
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公开(公告)号：US20220270922A1
公开(公告)日：2022-08-25
申请号：US17411094
申请日：2021-08-25
发明人： Tao CHEN
IPC分类号： H01L21/768 , H01L21/3213 , H01L21/285 , H01L21/762 , H01L23/522 , C23C14/58
摘要： This application relates to a memory device and a method for manufacturing the same, including: a substrate on which an insulation structure and a plurality of first active structures are formed is provided. The plurality of first active structures are arranged at intervals in the insulation structure. A word line conductive layer is formed on the substrate by a physical vapor deposition process. The word line conductive layer is patterned and etched to obtain a plurality of word line structures arranged in parallel and at intervals and filling slots located between adjacent word line structures. The filling slots comprise first filling slots that expose both parts of top surfaces of the first active structures and parts of the top surface of the insulation structure. Second active structures are formed in the first filling slots, and isolation structures are formed in the first filling slots.
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公开(公告)号：US20220077160A1
公开(公告)日：2022-03-10
申请号：US17401551
申请日：2021-08-13
发明人： Tao CHEN
IPC分类号： H01L27/108 , H01L21/762
摘要： The disclosure provides a method for manufacturing a semiconductor device. The method includes the following operations. A substrate on which an active region and a shallow trench isolation structure are formed, is provided. A first isolation layer is formed in the active region by an ion-doping technique. The active region surrounded by the first isolation layer is ion-implanted to form a first wordline structure. A second wordline structure is formed in the shallow trench isolation structure, and the first wordline structure and the second wordline structure are connected to form a buried wordline structure extending along a surface of the substrate.
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公开(公告)号：US20220077158A1
公开(公告)日：2022-03-10
申请号：US17391195
申请日：2021-08-02
发明人： Tao CHEN , ZhiCheng SHI
IPC分类号： H01L27/108 , H01L29/78 , H01L29/66 , G11C11/408
摘要： A semiconductor structure includes: a base substrate; an insulator, located on one side of the base substrate; bit lines, arranged in the insulator, the bit lines being distributed at intervals along first direction and extending along second direction; active bodies, located in the insulator, the active bodies being located on sides of respective bit lines facing away from the base substrate, orthographic projection of each active body on the base substrate at least partially coinciding with the orthographic projection of a respective bit line on the base substrate, and the active bodies being distributed at intervals along second direction; and word lines, located in the insulator and located on sides of respective bit lines facing away from the base substrate, the word lines being distributed at intervals along second direction and extending along first direction, and only one word line being arranged between two adjacent active bodies in second direction.
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公开(公告)号：US20230187448A1
公开(公告)日：2023-06-15
申请号：US17604991
申请日：2021-06-02
IPC分类号： H01L27/12 , H01L21/762 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/84
摘要： A semiconductor structure includes a semiconductor substrate, a first isolation dam, a plurality of switching transistors and a second isolation dam. The semiconductor substrate includes a trench, an isolation region formed by a region where the trench is located, a plurality of active regions defined by the isolation region, and an electrical isolation layer, the electrical isolation layer being located on one side, away from an opening of the trench, of the trench; the first isolation dam fills the trench; the switching transistor is at least partially embedded in the active region of the semiconductor substrate; and the second isolation dam is at least partially located between the first isolation dam and the electrical isolation layer.
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公开(公告)号：US20220285363A1
公开(公告)日：2022-09-08
申请号：US17460988
申请日：2021-08-30
发明人： Mengzhu QIAO , Tao CHEN
IPC分类号： H01L27/108
摘要： The present application provides a memory and a memory fabricating method. The memory includes a substrate, on which is disposed a separation layer, in which are arranged plural bitlines spaced apart from one another, the plural bitlines are arranged along a first direction, and each bitline is S-shaped. The method of fabricating the memory comprises the following steps: providing a substrate; forming on the substrate plural bitline grooves; forming in each bitline groove a first separation layer; forming bitlines on the first separation layer; forming a second separation layer on the bitlines; removing the substrate between adjacent separation walls, the separation wall including the first separation layer, the bitlines, and the second separation layer; and forming a third separation layer in a space between the adjacent separation walls, the third separation layer, the second separation layer, and the first separation layer together forming a separation layer.
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