公开(公告)号：US20220352177A1

公开(公告)日：2022-11-03

申请号：US17600828

申请日：2021-06-30

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Junchao ZHANG ,  Tao CHEN

IPC分类号： H01L27/108 ,  H01L29/66 ,  H01L21/302

摘要： A manufacturing method for memory includes: providing a substrate, and forming a first isolation layer and discrete bit lines on the substrate; removing part of the first isolation layer by a thickness to form discrete first trenches; forming word lines filling the first trenches, wherein the word lines each has a first side wall and a second side wall opposite to each other; forming discrete through holes each being between adjacent word lines; forming a first dielectric layer on surface of exposed first side wall, and forming a second dielectric layer on surface of exposed second side wall; and forming an active layer filling the through holes.

公开(公告)号：US20220310782A1

公开(公告)日：2022-09-29

申请号：US17593034

申请日：2021-04-12

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Junchao ZHANG ,  Cheng Yeh HSU

IPC分类号： H01L29/06 ,  H01L21/762 ,  H01L21/8234

摘要： A method for forming a semiconductor structure includes: providing a semiconductor substrate, the surface of the semiconductor substrate having a plurality of active areas and shallow trench isolation areas arranged in a first direction; etching the active areas and the shallow trench isolation areas in a direction perpendicular to the first direction to form first recesses and second recesses; covering the surfaces of the first recesses and the second recesses with an adhesive layer and a metal layer; and secondarily etching the metal layer and the adhesive layer in the direction perpendicular to the first direction to form a contact hole, the depth of the adhesive layer in the contact hole being defined as H2.