公开(公告)号：US07517742B2

公开(公告)日：2009-04-14

申请号：US11158021

申请日：2005-06-21

Applicant: Byoung W. Min ,  Laegu Kang ,  Michael Khazhinsky

Inventor： Byoung W. Min ,  Laegu Kang ,  Michael Khazhinsky

IPC: H01L21/20

CPC classification number: H01L21/84 ,  H01L27/0255 ,  H01L27/1203

Abstract: A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor stack is provided which includes a semiconductor substrate, a first semiconductor layer, and a first dielectric layer disposed between the substrate and the first semiconductor layer. A first trench is formed in the first dielectric layer which exposes a portion of the substrate, and a first implant region is formed in the first trench. Cathode and anode regions are formed in the first implant region.

Abstract translation: 本发明提供制造半导体器件的方法。 根据该方法，提供一种半导体堆叠，其包括半导体衬底，第一半导体层和设置在衬底和第一半导体层之间的第一电介质层。 在第一电介质层中形成第一沟槽，其暴露衬底的一部分，并且在第一沟槽中形成第一注入区域。 阴极和阳极区域形成在第一植入区域中。

公开(公告)号：US07186596B2

公开(公告)日：2007-03-06

申请号：US11158022

申请日：2005-06-21

Applicant: Byoung W. Min ,  Laegu Kang ,  Michael Khazhinsky

Inventor： Byoung W. Min ,  Laegu Kang ,  Michael Khazhinsky

IPC: H01L29/72

CPC classification number: H01L29/8611 ,  H01L27/0255 ,  H01L29/66136 ,  H01L29/868

Abstract: A method for making a semiconductor device is provided. The method comprises (a) providing a semiconductor stack comprising a semiconductor substrate (203), a first semiconductor layer (205), and a first dielectric layer (207) disposed between the substrate and the first semiconductor layer; (b) forming a first trench in the first dielectric layer which exposes a portion of the substrate; (c) forming a first doped region (209) in the exposed portion of the substrate; and (d) forming anode (211) and cathode (213) regions in the first implant region.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括（a）提供包括半导体衬底（203），第一半导体层（205）和设置在衬底和第一半导体层之间的第一电介质层（207）的半导体堆叠; （b）在所述第一电介质层中形成暴露所述衬底的一部分的第一沟槽; （c）在所述衬底的暴露部分中形成第一掺杂区域（209）; 和（d）在第一注入区域中形成阳极（211）和阴极（213）区域。

公开(公告)号：US06724048B2

公开(公告)日：2004-04-20

申请号：US10462178

申请日：2003-06-16

Applicant: Byoung W. Min ,  Michael A. Mendicino ,  Laegu Kang

Inventor： Byoung W. Min ,  Michael A. Mendicino ,  Laegu Kang

IPC: H01L2100

CPC classification number: H01L29/42384 ,  H01L29/7841

Abstract: An integrated circuit using silicon-on-insulator (SOI) has most of its transistors with their channels (bodies) floating. Some of the transistors, however, must have their channels coupled to a predetermined bias in order to achieve desired operating characteristics. In order to achieve the needed bias, a contact path is provided in the semiconductor layer of the SOI substrate and under an extension of the gate of the transistor. The extension is separated from the semiconductor layer by an insulator that is thicker than that for most of the transistor but advantageously is the same as that used for some of the thick gate insulator devices used, typically, for high voltage applications. This thicker insulator advantageously reduces the capacitance, but does not increase process complexity because it uses an insulator already required by the process.

Abstract translation: 使用绝缘体上硅（SOI）的集成电路的大多数晶体管的通道（体）浮动。 然而，一些晶体管必须使其沟道耦合到预定的偏压，以便实现期望的操作特性。 为了获得所需的偏置，在SOI衬底的半导体层中和在晶体管的栅极的延伸下提供接触路径。 该延伸部分通过绝缘体与半导体层分离，该绝缘体比大多数晶体管的绝缘体更厚，但有利地与用于一般用于高电压应用的一些厚栅极绝缘体器件相同。 这种较厚的绝缘体有利地减小电容，但是不会增加工艺的复杂性，因为它使用了该工艺已经需要的绝缘体。

公开(公告)号：US06620656B2

公开(公告)日：2003-09-16

申请号：US10024916

申请日：2001-12-19

Applicant: Byoung W. Min ,  Michael A. Mendicino ,  Laegu Kang

Inventor： Byoung W. Min ,  Michael A. Mendicino ,  Laegu Kang

IPC: H01L2100

CPC classification number: H01L29/42384 ,  H01L29/7841

Abstract: An integrated circuit using silicon-on-insulator (SOI) has most of its transistors with their channels (bodies) floating. Some of the transistors, however, must have their channels coupled to a predetermined bias in order to achieve desired operating characteristics. In order to achieve the needed bias, a contact path is provided in the semiconductor layer of the SOI substrate and under an extension of the gate of the transistor. The extension is separated from the semiconductor layer by an insulator that is thicker than that for most of the transistor but advantageously is the same as that used for some of the thick gate insulator devices used, typically, for high voltage applications. This thicker insulator advantageously reduces the capacitance, but does not increase process complexity because it uses an insulator already required by the process.

Abstract translation: 使用绝缘体上硅（SOI）的集成电路的大多数晶体管的通道（体）浮动。 然而，一些晶体管必须使其沟道耦合到预定的偏压，以便实现期望的操作特性。 为了获得所需的偏置，在SOI衬底的半导体层中和在晶体管的栅极的延伸下提供接触路径。 该延伸部分通过绝缘体与半导体层分离，该绝缘体比大多数晶体管的绝缘体更厚，但有利地与用于一般用于高电压应用的一些厚栅极绝缘体器件相同。 这种较厚的绝缘体有利地减小电容，但是不会增加工艺的复杂性，因为它使用了该工艺已经需要的绝缘体。

公开(公告)号：US20110012629A1

公开(公告)日：2011-01-20

申请号：US12503116

申请日：2009-07-15

Applicant: Satya N. Chakravarti ,  Dechao Guo ,  Chuck T. Le ,  Byoung W. Min ,  Rajeevakumar V. Thekkemadathil ,  Keith Kwong Hon Wong

Inventor： Satya N. Chakravarti ,  Dechao Guo ,  Chuck T. Le ,  Byoung W. Min ,  Rajeevakumar V. Thekkemadathil ,  Keith Kwong Hon Wong

IPC: G01R27/08 ,  H01L27/06 ,  H01L21/28 ,  H01H37/76

CPC classification number: H01L27/0617 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).

Abstract translation: 在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。 第一导电材料层和无定形金属氧化物沉积到凹陷区域中。 第二导电材料层填充凹部。 在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。 为了编程电反熔丝，电流在一对导电触头中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。 感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。

公开(公告)号：US07709303B2

公开(公告)日：2010-05-04

申请号：US11328668

申请日：2006-01-10

Applicant: James D. Burnett ,  Leo Mathew ,  Byoung W. Min

Inventor： James D. Burnett ,  Leo Mathew ,  Byoung W. Min

IPC: H01L21/00

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A process for forming an electronic device can include forming a semiconductor fin of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin is shortened to a second height. In accordance with specific embodiment a second semiconductor fin can be formed, each of the first and the second semiconductor fins having a different height representing a channel width. In accordance with another specific embodiment a second and a third semiconductor fin can be formed, each of the first, the second and the third semiconductor fins having a different height representing a channel width.

Abstract translation: 用于形成电子器件的工艺可以包括形成用于鳍型结构的第一高度的半导体鳍片，并且去除半导体鳍片的一部分，使得半导体鳍片缩短到第二高度。 根据具体实施例，可以形成第二半导体鳍片，第一和第二半导体鳍片中的每一个具有表示沟道宽度的不同高度。 根据另一具体实施例，可以形成第二和第三半导体鳍片，第一，第二和第三半导体鳍片中的每一个具有代表沟道宽度的不同高度。

公开(公告)号：US20100078727A1

公开(公告)日：2010-04-01

申请号：US12243313

申请日：2008-10-01

Applicant: Byoung W. Min ,  Satya N. Chakravarti

Inventor： Byoung W. Min ,  Satya N. Chakravarti

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/44

CPC classification number: H01L21/84 ,  H01L23/5228 ,  H01L23/5256 ,  H01L27/0629 ,  H01L27/1203 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor fabrication process and apparatus are provided for forming passive devices, such as a fuse (93) or resistor (95), in an active substrate region (103) by using heavy ion implantation (30) and annealing (40) to selectively form polycrystalline structures (42, 44) from a monocrystalline active layer (103), while retaining the single crystalline regions in the active layer (103) for use in forming active devices, such as NMOS and/or PMOS transistors (94). As disclosed, fuse structures (93) may be fabricated by forming silicide (90) in an upper region of the polycrystalline structure (42), while resistor structures (95) may be simultaneously formed from polycrystalline structure (44) which is selectively masked during silicide formation.

Abstract translation: 提供半导体制造工艺和装置，用于通过使用重离子注入（30）和退火（40）在有源衬底区域（103）中形成无源器件，例如熔丝（93）或电阻器（95），以选择性地形成 同时保持有源层（103）中的单晶区域用于形成诸如NMOS和/或PMOS晶体管（94）的有源器件的单晶有源层（103）的多晶结构（42,44）。 如所公开的那样，可以通过在多晶结构（42）的上部区域中形成硅化物（90）来制造熔丝结构（93），而电阻器结构（95）可以由多晶结构（44）同时形成，多晶结构（44）在 硅化物形成。

公开(公告)号：US06921961B2

公开(公告)日：2005-07-26

申请号：US10946758

申请日：2004-09-22

Applicant: Hector Sanchez ,  Michael A. Mendicino ,  Byoung W. Min ,  Kathleen C. Yu

Inventor： Hector Sanchez ,  Michael A. Mendicino ,  Byoung W. Min ,  Kathleen C. Yu

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L23/522 ,  H01L27/06 ,  H01L27/12 ,  H01L29/00 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L27/0688 ,  H01L21/76838 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.

Abstract translation: 半导体（10）具有诸如晶体管的有源器件，其具有通过通孔或导电区域（52）和互连件（68）连接的直接下伏的无源器件（例如电容器）（75,77,79） ，99）。 通孔或导电区域（52）接触晶体管的扩散或源极区域（22）的底表面并与第一（75）电容器电极接触。 横向定位的垂直通孔（32,54,68）和互连件（99）接触电容器电极的第二（79）。 金属互连或导电材料（68）可以用作通过在晶体管下面实现功率平面而不是与晶体管相邻来节省电路面积的功率面。

公开(公告)号：US07927934B2

公开(公告)日：2011-04-19

申请号：US11734328

申请日：2007-04-12

Applicant: Byoung W. Min ,  Dharmesh Jawarani

Inventor： Byoung W. Min ,  Dharmesh Jawarani

IPC: H01L21/84

CPC classification number: H01L29/78615 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

Abstract: A method including providing a substrate and providing an insulating layer overlying the substrate is provided. The method further includes providing a body region comprising a body material overlying the insulating layer. The method further includes forming at least one transistor overlying the insulating layer, the at least one transistor having a source, a drain and a gate with a sidewall spacer, the sidewall spacer comprising a substantially uniform geometric shape around the gate, the gate overlying the body region. The method further includes forming a first silicide region within the source and a second silicide region within the drain, the first silicide region having a differing geometric shape than the second silicide region and being electrically conductive between the body region and the source.

Abstract translation: 提供了一种包括提供衬底和提供覆盖衬底的绝缘层的方法。 该方法还包括提供包括覆盖绝缘层的主体材料的主体区域。 所述方法还包括形成覆盖绝缘层的至少一个晶体管，所述至少一个晶体管具有源极，漏极和具有侧壁间隔物的栅极，所述侧壁间隔物包括围绕栅极的基本上均匀的几何形状，所述栅极覆盖 身体区域。 所述方法还包括在所述源极内形成第一硅化物区域和所述漏极内的第二硅化物区域，所述第一硅化物区域具有与所述第二硅化物区域不同的几何形状并且在所述体区域和所述源极之间导电。

公开(公告)号：US20080254586A1

公开(公告)日：2008-10-16

申请号：US11734328

申请日：2007-04-12

Applicant: Byoung W. Min ,  Dharmesh Jawarani

Inventor： Byoung W. Min ,  Dharmesh Jawarani

IPC: H01L21/336

CPC classification number: H01L29/78615 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

Abstract: A method including providing a substrate and providing an insulating layer overlying the substrate is provided. The method further includes providing a body region comprising a body material overlying the insulating layer. The method further includes forming at least one transistor overlying the insulating layer, the at least one transistor having a source, a drain and a gate with a sidewall spacer, the sidewall spacer comprising a substantially uniform geometric shape around the gate, the gate overlying the body region. The method further includes forming a first silicide region within the source and a second silicide region within the drain, the first silicide region having a differing geometric shape than the second silicide region and being electrically conductive between the body region and the source.

Abstract translation: 提供了一种包括提供衬底和提供覆盖衬底的绝缘层的方法。 该方法还包括提供包括覆盖绝缘层的主体材料的主体区域。 所述方法还包括形成覆盖绝缘层的至少一个晶体管，所述至少一个晶体管具有源极，漏极和具有侧壁间隔物的栅极，所述侧壁间隔物包括围绕栅极的基本上均匀的几何形状，所述栅极覆盖 身体区域。 所述方法还包括在所述源极内形成第一硅化物区域和所述漏极内的第二硅化物区域，所述第一硅化物区域具有与所述第二硅化物区域不同的几何形状并且在所述体区域和所述源极之间导电。