公开(公告)号：US20160064539A1

公开(公告)日：2016-03-03

申请号：US14442546

申请日：2013-11-15

Applicant: Bin Lu ,  Min Sun ,  Tomas Palacios

Inventor： Bin Lu ,  Min Sun ,  Tomas Palacios

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L21/306 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7787 ,  H01L21/30612 ,  H01L21/30621 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor structure has a first layer that includes a first semiconductor material and a second layer that includes a second semiconductor material. The first semiconductor material is selectively etchable over the second semiconductor material using a first etching process. The first layer is disposed over the second layer. A recess is disposed at least in the first layer. Also described is a method of forming a semiconductor structure that includes a recess. The method includes etching a region in a first layer using a first etching process. The first layer includes a first semiconductor material. The first etching process stops at a second layer beneath the first layer. The second layer includes a second semiconductor material.

Abstract translation: 半导体结构具有包括第一半导体材料的第一层和包括第二半导体材料的第二层。 第一半导体材料可以使用第一蚀刻工艺在第二半导体材料上选择性地蚀刻。 第一层设置在第二层上。 凹部至少设置在第一层中。 还描述了形成包括凹部的半导体结构的方法。 该方法包括使用第一蚀刻工艺蚀刻第一层中的区域。 第一层包括第一半导体材料。 第一蚀刻工艺在第一层下面的第二层停止。 第二层包括第二半导体材料。

公开(公告)号：US08587031B2

公开(公告)日：2013-11-19

申请号：US13557414

申请日：2012-07-25

Applicant: Bin Lu ,  Tomas Palacios

Inventor： Bin Lu ,  Tomas Palacios

IPC: H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/4236

Abstract: A dual-gate normally-off nitride transistor that includes a first gate structure formed between a source electrode and a drain electrode for controlling a normally-off channel region of the dual-gate normally-off nitride transistor. A second gate structure is formed between the first gate structure and the drain electrode for modulating a normally-on channel region underneath the second gate structure. The magnitude of the threshold voltage of the second gate structure is smaller than the drain breakdown of the first gate structure for proper operation of the dual-gate normally-off nitride transistor.

Abstract translation: 一种双栅极常关氮化物晶体管，其包括形成在源电极和漏电极之间的第一栅极结构，用于控制双栅极正常氮化物晶体管的常关沟道区。 在第一栅极结构和漏极之间形成第二栅极结构，用于调制在第二栅极结构下方的常导通道区域。 第二栅极结构的阈值电压的幅度小于用于双栅极常关氮化物晶体管的正常工作的第一栅极结构的漏极击穿。

公开(公告)号：US20130020614A1

公开(公告)日：2013-01-24

申请号：US13557414

申请日：2012-07-25

Applicant: Bin Lu ,  Tomas Palacios

Inventor： Bin Lu ,  Tomas Palacios

IPC: H01L29/778 ,  H01L21/336

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/4236

Abstract: A dual-gate normally-off nitride transistor that includes a first gate structure formed between a source electrode and a drain electrode for controlling a normally-off channel region of the dual-gate normally-off nitride transistor. A second gate structure is formed between the first gate structure and the drain electrode for modulating a normally-on channel region underneath the second gate structure. The magnitude of the threshold voltage of the second gate structure is smaller than the drain breakdown of the first gate structure for proper operation of the dual-gate normally-off nitride transistor.

Abstract translation: 一种双栅极常关氮化物晶体管，其包括形成在源电极和漏电极之间的第一栅极结构，用于控制双栅极正常氮化物晶体管的常关沟道区。 在第一栅极结构和漏极之间形成第二栅极结构，用于调制在第二栅极结构下方的常导通道区域。 第二栅极结构的阈值电压的幅度小于用于双栅极常关氮化物晶体管的正常工作的第一栅极结构的漏极击穿。

公开(公告)号：US20100084688A1

公开(公告)日：2010-04-08

申请号：US12574146

申请日：2009-10-06

Applicant: Bin Lu ,  Tomas Palacios

Inventor： Bin Lu ,  Tomas Palacios

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/7788 ,  H01L29/2003 ,  H01L29/51 ,  H01L29/7787

Abstract: A heterojunction for use in a transistor structure is provided. The heterojunction includes a barrier layer positioned beneath a gate region of the transistor structure. The barrier layer includes nitride-based semiconductor materials. A channel layer provides electrical conduction An intermediate layer near the barrier layer and including nitride-based semiconductor materials having a wider bandgap than the channel layer

Abstract translation: 提供了一种用于晶体管结构的异质结。 异质结包括位于晶体管结构的栅极区域下方的势垒层。 阻挡层包括氮化物基半导体材料。 沟道层提供电传导在阻挡层附近的中间层，并且包括具有比沟道层更宽的带隙的氮化物基半导体材料

公开(公告)号：US08188459B2

公开(公告)日：2012-05-29

申请号：US12577892

申请日：2009-10-13

Applicant: Tomas Palacios ,  Jinwook Chung

Inventor： Tomas Palacios ,  Jinwook Chung

IPC: H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L29/66462 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/7783 ,  H01L29/7787

Abstract: A nitride-based semiconductor device is provided. The nitride-base semiconductor device includes a substrate comprising one or more locally etched regions and a buffer layer comprising one or multiple InAlGaN layers on the substrate. A channel layer includes GaN on the buffer layer. A barrier layer includes one or multiple AlGaN layers on the channel layer.

Abstract translation: 提供了一种氮化物基半导体器件。 氮化物基半导体器件包括包括一个或多个局部蚀刻区域的衬底和在衬底上包括一个或多个InAlGaN层的缓冲层。 沟道层在缓冲层上包括GaN。 阻挡层包括沟道层上的一个或多个AlGaN层。

公开(公告)号：US20100032717A1

公开(公告)日：2010-02-11

申请号：US12577892

申请日：2009-10-13

Applicant: Tomas Palacios ,  Jinwook Chung

Inventor： Tomas Palacios ,  Jinwook Chung

IPC: H01L29/778 ,  H01L29/205 ,  H01L21/335

CPC classification number: H01L29/66462 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/7783 ,  H01L29/7787

Abstract: A nitride-based semiconductor device is provided. The nitride-base semiconductor device includes a substrate comprising one or more locally etched regions and a buffer layer comprising one or multiple InAlGaN layers on the substrate. A channel layer includes GaN on the buffer layer. A barrier layer includes one or multiple AlGaN layers on the channel layer.

Abstract translation: 提供了一种氮化物基半导体器件。 氮化物基半导体器件包括包括一个或多个局部蚀刻区域的衬底和在衬底上包括一个或多个InAlGaN层的缓冲层。 沟道层在缓冲层上包括GaN。 阻挡层包括沟道层上的一个或多个AlGaN层。

公开(公告)号：US08703623B2

公开(公告)日：2014-04-22

申请号：US12475740

申请日：2009-06-01

Applicant: Jinwook Chung ,  Han Wang ,  Tomas Palacios

Inventor： Jinwook Chung ,  Han Wang ,  Tomas Palacios

IPC: H01L21/31 ,  H01L21/469 ,  H01L31/101

CPC classification number: H01L21/8258 ,  H01L21/2007 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/7781 ,  H01L29/7787

Abstract: A semiconductor arrangement is provided that includes one or more substrate structures. One or more nitride-based material structures are used in fabricating nitride-based devices. One or more intermediary layers are interposed between the one or more substrate structures and the one or more nitride-based material structures. The one or more intermediary layers support the lattice mismatch and thermal expansion coefficients between the one or more nitride-based material structure and the one or more substrate structures. Several new electronic devices based on this arrangement are described.

Abstract translation: 提供了包括一个或多个衬底结构的半导体布置。 一种或多种基于氮化物的材料结构用于制造基于氮化物的器件。 一个或多个中间层插入在一个或多个衬底结构和一个或多个基于氮化物的材料结构之间。 一个或多个中间层支持一种或多种基于氮化物的材料结构与一种或多种衬底结构之间的晶格失配和热膨胀系数。 描述了基于这种布置的几种新的电子设备。

公开(公告)号：US08114717B2

公开(公告)日：2012-02-14

申请号：US11599874

申请日：2006-11-15

Applicant: Tomas Palacios ,  Likun Shen ,  Umesh K. Mishra

Inventor： Tomas Palacios ,  Likun Shen ,  Umesh K. Mishra

IPC: H01L21/335

CPC classification number: H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L33/0095

Abstract: A fluorine treatment that can shape the electric field profile in electronic devices in 1, 2, or 3 dimensions is disclosed. A method to increase the breakdown voltage of AlGaN/GaN high electron mobility transistors, by the introduction of a controlled amount of dispersion into the device, is also disclosed. This dispersion is large enough to reduce the peak electric field in the channel, but low enough in order not to cause a significant decrease in the output power of the device. In this design, the whole transistor is passivated against dispersion with the exception of a small region 50 to 100 nm wide right next to the drain side of the gate. In that region, surface traps cause limited amounts of dispersion, that will spread the high electric field under the gate edge, therefore increasing the breakdown voltage. Three different methods to introduce dispersion in the 50 nm closest to the gate are described: (1) introduction of a small gap between the passivation and the gate metal, (2) gradually reducing the thickness of the passivation, and (3) gradually reducing the thickness of the AlGaN cap layer in the region close the gate.

Abstract translation: 公开了可以在1,2或3维度的电子设备中形成电场分布的氟处理。 还公开了通过将受控量的分散引入到器件中来增加AlGaN / GaN高电子迁移率晶体管的击穿电压的方法。 该色散足够大以减少通道中的峰值电场，但是足够低以便不会导致器件的输出功率的显着降低。 在该设计中，整个晶体管被钝化以抵消色散，除了在栅极的漏极侧旁边的50至100nm宽的小区域之外。 在该区域中，表面捕集器产生有限的色散，这将扩散栅极边缘处的高电场，从而增加击穿电压。 描述了在最接近栅极的50nm中引入色散的三种不同的方法：（1）在钝化和栅极金属之间引入小的间隙，（2）逐渐减小钝化的厚度，和（3）逐渐降低 在关闭栅极的区域中的AlGaN覆盖层的厚度。

公开(公告)号：US20070224710A1

公开(公告)日：2007-09-27

申请号：US11599874

申请日：2006-11-15

Applicant: Tomas Palacios ,  Likun Shen ,  Umesh Mishra

Inventor： Tomas Palacios ,  Likun Shen ,  Umesh Mishra

IPC: H01L21/00 ,  H01L21/335

CPC classification number: H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L33/0095

Abstract: A fluorine treatment that can shape the electric field profile in electronic devices in 1, 2, or 3 dimensions is disclosed. A method to increase the breakdown voltage of AlGaN/GaN high electron mobility transistors, by the introduction of a controlled amount of dispersion into the device, is also disclosed. This dispersion is large enough to reduce the peak electric field in the channel, but low enough in order not to cause a significant decrease in the output power of the device. In this design, the whole transistor is passivated against dispersion with the exception of a small region 50 to 100 nm wide right next to the drain side of the gate. In that region, surface traps cause limited amounts of dispersion, that will spread the high electric field under the gate edge, therefore increasing the breakdown voltage. Three different methods to introduce dispersion in the 50 nm closest to the gate are described: (1) introduction of a small gap between the passivation and the gate metal, (2) gradually reducing the thickness of the passivation, and (3) gradually reducing the thickness of the AlGaN cap layer in the region close the gate.

Abstract translation: 公开了可以在1,2或3维度的电子设备中形成电场分布的氟处理。 还公开了通过将受控量的分散引入到器件中来增加AlGaN / GaN高电子迁移率晶体管的击穿电压的方法。 该色散足够大以减少通道中的峰值电场，但是足够低以便不会导致器件的输出功率的显着降低。 在该设计中，整个晶体管被钝化以抵消色散，除了在栅极的漏极侧旁边的50至100nm宽的小区域之外。 在该区域中，表面捕集器产生有限的色散，这将扩散栅极边缘处的高电场，从而增加击穿电压。 描述了在最接近栅极的50nm中引入色散的三种不同的方法：（1）在钝化和栅极金属之间引入小的间隙，（2）逐渐减小钝化的厚度，和（3）逐渐降低 在关闭栅极的区域中的AlGaN覆盖层的厚度。

公开(公告)号：US20100301347A1

公开(公告)日：2010-12-02

申请号：US12475740

申请日：2009-06-01

Applicant: Jinwook Chung ,  Han Wang ,  Tomas Palacios

Inventor： Jinwook Chung ,  Han Wang ,  Tomas Palacios

IPC: H01L29/20 ,  H01L21/18

CPC classification number: H01L21/8258 ,  H01L21/2007 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/7781 ,  H01L29/7787

Abstract: A semiconductor arrangement is provided that includes one or more substrate structures. One or more nitride-based material structures are used in fabricating nitride-based devices. One or more intermediary layers are interposed between the one or more substrate structures and the one or more nitride-based material structures. The one or more intermediary layers support the lattice mismatch and thermal expansion coefficients between the one or more nitride-based material structure and the one or more substrate structures. Several new electronic devices based on this arrangement are described.

Abstract translation: 提供了包括一个或多个衬底结构的半导体布置。 一种或多种基于氮化物的材料结构用于制造基于氮化物的器件。 一个或多个中间层插入在一个或多个衬底结构和一个或多个氮化物基材料结构之间。 一个或多个中间层支持一种或多种基于氮化物的材料结构与一种或多种衬底结构之间的晶格失配和热膨胀系数。 描述了基于这种布置的几种新的电子设备。