公开(公告)号：US08207615B2

公开(公告)日：2012-06-26

申请号：US13010478

申请日：2011-01-20

Applicant: Bai-Yao Lou ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Bai-Yao Lou ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L27/14618 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2924/1461 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package, which includes a substrate having an upper surface and a lower surface, a chip disposed in or on the substrate, a pad disposed in or on the substrate and electrically connected to the chip, a hole extending from the lower surface toward the upper surface, exposing the pad, wherein a lower opening of the hole near the lower surface has a width that is shorter than that of an upper opening of the hole near the upper surface, an insulating layer located overlying a sidewall of the hole, and a conducting layer located overlying the insulating layer and electrically connected to the pad.

Abstract translation: 本发明的实施例提供了一种芯片封装，其包括具有上表面和下表面的基板，设置在基板中或基板上的芯片，设置在基板中或基板上并与芯片电连接的焊盘， 从下表面向上表面露出焊盘，其中靠近下表面的孔的下开口具有比上表面附近的孔的上开口短的宽度，绝缘层位于 孔的侧壁，以及位于绝缘层上方并电连接到焊盘的导电层。

公开(公告)号：US20110175236A1

公开(公告)日：2011-07-21

申请号：US13010478

申请日：2011-01-20

Applicant: Bai-Yao LOU ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Bai-Yao LOU ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L27/14618 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2924/1461 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package, which includes a substrate having an upper surface and a lower surface, a chip disposed in or on the substrate, a pad disposed in or on the substrate and electrically connected to the chip, a hole extending from the lower surface toward the upper surface, exposing the pad, wherein a lower opening of the hole near the lower surface has a width that is shorter than that of an upper opening of the hole near the upper surface, an insulating layer located overlying a sidewall of the hole, and a conducting layer located overlying the insulating layer and electrically connected to the pad.

Abstract translation: 本发明的实施例提供了一种芯片封装，其包括具有上表面和下表面的基板，设置在基板中或基板上的芯片，设置在基板中或基板上并与芯片电连接的焊盘， 从下表面向上表面露出焊盘，其中靠近下表面的孔的下开口具有比上表面附近的孔的上开口短的宽度，绝缘层位于 孔的侧壁，以及位于绝缘层上方并电连接到焊盘的导电层。

公开(公告)号：US20110221070A1

公开(公告)日：2011-09-15

申请号：US13044457

申请日：2011-03-09

Applicant: Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/561 ,  H01L21/76805 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface thereof, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads.

公开(公告)号：US09559001B2

公开(公告)日：2017-01-31

申请号：US13024156

申请日：2011-02-09

Applicant: Yu-Lin Yen ,  Ming-Kun Yang ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Yu-Lin Yen ,  Ming-Kun Yang ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763 ,  H01L23/58 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/486 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/05 ,  H01L2224/0501 ,  H01L2224/0557 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552

Abstract: According to an embodiment of the invention, a chip package is provided, which includes: a substrate having an upper surface and a lower surface; a hole extending from the upper surface toward the lower surface; an insulating layer located overlying a sidewall of the hole; and a material layer located overlying the sidewall of the hole, wherein the material layer is separated from the upper surface of the substrate by a distance and a thickness of the material layer decreases along a direction toward the lower surface.

Abstract translation: 根据本发明的实施例，提供了一种芯片封装，其包括：具有上表面和下表面的基板; 从上表面向下表面延伸的孔; 位于所述孔的侧壁上方的绝缘层; 以及位于所述孔的侧壁上方的材料层，其中所述材料层与所述基板的上表面分离一定距离，并且所述材料层的厚度沿着朝向所述下表面的方向减小。

公开(公告)号：US08692382B2

公开(公告)日：2014-04-08

申请号：US13190388

申请日：2011-07-25

Applicant: Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/48

CPC classification number: H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/13025 ,  H01L2224/9202 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein an upper sidewall of the hole inclines to the lower surface of the substrate, and a lower sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

Abstract translation: 根据本发明的实施例，提供了芯片封装。 芯片封装包括：具有上表面和下表面的基板; 位于所述基板的下表面下方的多个导电垫; 位于导电垫之间的电介质层; 从衬底的上表面延伸到下表面的沟槽; 从所述沟槽的底部延伸到所述衬底的下表面的孔，其中所述孔的上侧壁倾斜到所述衬底的下表面，并且所述孔的下侧壁或底部暴露所述导电垫的一部分 ; 以及导电层，其位于所述孔中并电连接到至少一个所述导电焊盘。

公开(公告)号：US08552565B2

公开(公告)日：2013-10-08

申请号：US13204603

申请日：2011-08-05

Applicant: Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/561 ,  H01L21/76805 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located under the lower surface of the substrate, and a dielectric layer located between the conducting pads. A hole is provided in the substrate, which extends from the upper surface towards the lower surface of the substrate. A sidewall or a bottom of the hole exposes a portion of the conducting pads. The upper opening of the hole near the upper surface is smaller than a lower opening of the hole near the lower surface. An upper conducting pad has at least an opening or a trench exposing a lower conducting pad of the conducting pads. A conducting layer is disposed in the hole, which electrically contacting at least one of the conducting pads.

Abstract translation: 芯片封装包括具有上表面和下表面的衬底，位于衬底的下表面下方的多个导电衬垫以及位于导电焊盘之间的电介质层。 在衬底中设置有一个孔，该孔从衬底的上表面向下表面延伸。 孔的侧壁或底部暴露出导电垫的一部分。 上表面附近的孔的上部开口小于靠近下表面的孔的下部开口。 上导电焊盘至少具有暴露导电焊盘的下导电焊盘的开口或沟槽。 导电层设置在孔中，该导电层与至少一个导电垫电接触。

公开(公告)号：US20110291153A1

公开(公告)日：2011-12-01

申请号：US13118602

申请日：2011-05-31

Applicant: Ming-Kun Yang ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Ming-Kun Yang ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L33/48

CPC classification number: H01L33/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/73 ,  H01L33/62 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/12041 ,  H01L2933/0066 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A light-emitting diode submount includes a base, a through silicon via and a sealing layer. The base has a die side and a back side. The through silicon via penetrates the base to connect the die side and the back side. The through silicon via includes a conoidal-shaped portion converging from the back side toward the die side, and a vertical via portion connects with the conoidal-shaped portion. A sealing layer seals the vertical via portion.

Abstract translation: 发光二极管基座包括基底，穿硅通孔和密封层。 基座具有模具侧和背面。 贯通硅通孔穿透底座以连接模具侧和背面。 贯通硅通孔包括从后侧朝向管芯侧会聚的圆锥形部分，并且垂直通孔部分与锥形部分连接。 密封层密封垂直通孔部分。

公开(公告)号：US08698316B2

公开(公告)日：2014-04-15

申请号：US13190408

申请日：2011-07-25

Applicant: Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/48

CPC classification number: H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L2221/68377 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein a sidewall of the hole is substantially perpendicular to the lower surface of the substrate, and the sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

Abstract translation: 根据本发明的实施例，提供了芯片封装。 芯片封装包括：具有上表面和下表面的基板; 位于所述基板的下表面下方的多个导电焊盘; 位于导电垫之间的电介质层; 从衬底的上表面延伸到下表面的沟槽; 从所述沟槽的底部延伸到所述衬底的下表面的孔，其中所述孔的侧壁基本上垂直于所述衬底的下表面，并且所述孔的侧壁或所述底部露出所述导电垫的一部分 ; 以及导电层，其位于所述孔中并电连接到至少一个所述导电焊盘。

公开(公告)号：US08525345B2

公开(公告)日：2013-09-03

申请号：US13044457

申请日：2011-03-09

Applicant: Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/561 ,  H01L21/76805 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface thereof, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads.

Abstract translation: 根据本发明的实施例，提供了芯片封装。 芯片封装包括具有上表面和下表面的衬底，位于衬底中或其下表面下方的多个导电焊盘，位于导电焊盘之间的介电层，从上表面向下延伸的孔 表面并暴露一部分导电焊盘，以及导电层，其位于孔中并与导电焊盘电接触。

公开(公告)号：US20110193241A1

公开(公告)日：2011-08-11

申请号：US13024156

申请日：2011-02-09

Applicant: Yu-Lin YEN ,  Ming-Kun Yang ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Yu-Lin YEN ,  Ming-Kun Yang ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/486 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/05 ,  H01L2224/0501 ,  H01L2224/0557 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552

Abstract: According to an embodiment of the invention, a chip package is provided, which includes: a substrate having an upper surface and a lower surface; a hole extending from the upper surface toward the lower surface; an insulating layer located overlying a sidewall of the hole; and a material layer located overlying the sidewall of the hole, wherein the material layer is separated from the upper surface of the substrate by a distance and a thickness of the material layer decreases along a direction toward the lower surface.

Abstract translation: 根据本发明的实施例，提供了一种芯片封装，其包括：具有上表面和下表面的基板; 从上表面向下表面延伸的孔; 位于所述孔的侧壁上方的绝缘层; 以及位于所述孔的侧壁上方的材料层，其中所述材料层与所述基板的上表面分离一定距离，并且所述材料层的厚度沿着朝向所述下表面的方向减小。