公开(公告)号：US09413375B2

公开(公告)日：2016-08-09

申请号：US14586866

申请日：2014-12-30

Applicant: Broadcom Corporation

Inventor： Xicheng Jiang ,  Xinyu Yu ,  Fang Lin ,  Yee Ling Cheung ,  Michael Inerfield

IPC: H04B1/38 ,  H04B1/40 ,  H03M1/18 ,  H04B1/00 ,  H04B1/16 ,  H03M1/66 ,  H04M1/02

CPC classification number: H03M1/185 ,  H03M1/66 ,  H04B1/0003 ,  H04B1/1646 ,  H04B1/40 ,  H04M1/0202

Abstract: A CMOS analog and audio front-end circuit includes an enhanced analog-to-digital converter (ADC) that achieves a desired signal-to-noise-and-distortion (SNDR) and an analog-front-end transmit (TX) digital-to-analog converter (DAC). The enhanced ADC includes an improved single Op-Amp resonator coupled to a feed-forward loop and can substantially reduce signal transfer function (STF) peaking of the enhanced ADC. The CMOS analog and audio front-end circuit is integrated with a baseband processor.

Abstract translation: CMOS模拟和音频前端电路包括增强的模数转换器（ADC），其实现期望的信噪比失真（SNDR）和模拟前端发送（TX）数字 - 模数转换器（DAC）。 增强型ADC包括耦合到前馈环路的改进的单个运算放大器，可以显着降低增强型ADC的信号传递函数（STF）峰值。 CMOS模拟和音频前端电路与基带处理器集成在一起。

公开(公告)号：US08749425B1

公开(公告)日：2014-06-10

申请号：US13722388

申请日：2012-12-20

Applicant: Broadcom Corporation

Inventor： Jason Hu ,  Xinyu Yu ,  Jing Yang ,  Sumant Ranganathan

IPC: H03M1/12

CPC classification number: H03M1/0845

Abstract: An analog-to-digital converter (ADC) includes reference charge cancellation features to at least partially offset a voltage distortion on a bypass capacitor of a reference buffer due to a voltage reference hit taken by a switched capacitor bank with which the bypass capacitor is connected. The charge cancellation may be configured in logic to be input signal dependent because different resolved bits or transitions between resolved bits may cause different amounts of voltage reference hits. By adjusting the bypass capacitor in response to each of at least some of the reference hits while resolving a word of bits, the reference voltage signal provided by the bypass capacitor undergoes far less settling, remaining more stable and linear for a more accurate reference voltage. Furthermore, a smaller capacitor may be used for the bypass capacitor, reducing power consumption and area on chip.

Abstract translation: 模数转换器（ADC）包括参考电荷消除特征，以至少部分地偏移参考缓冲器的旁路电容器上的电压失真，这是由于旁路电容器连接的开关电容器组所引起的电压基准点 。 电荷消除可以被配置为逻辑以输入信号，因为解析的位之间的不同的分辨位或转换可能导致不同量的电压参考点。 通过在解析位字时响应于至少一些参考命中中的每一个来调节旁路电容器，由旁路电容器提供的参考电压信号经历较少的稳定度，对于更精确的参考电压而言保持更稳定和线性。 此外，旁路电容器可以使用较小的电容器，从而降低功耗和芯片上的面积。

公开(公告)号：US09577662B2

公开(公告)日：2017-02-21

申请号：US14954532

申请日：2015-11-30

Applicant: Broadcom Corporation

Inventor： Guowen Wei ,  Xinyu Yu ,  Michael Inerfield ,  Tom Kwan

IPC: H03M1/06 ,  H03M3/00 ,  H03M1/12 ,  H03M1/00 ,  H03M1/14 ,  H03M1/46 ,  H03M1/80

CPC classification number: H03M3/37 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/144 ,  H03M1/466 ,  H03M1/804 ,  H03M3/426

Abstract: A CT-SDADC of the present disclosure converts the analog input signal from a representation in an analog signal domain to a representation in a digital signal domain to provide the digital output signal. The CT-SDADC achieves the analog-to-digital conversion and ELDC by switching between two phases in the SAR sub-ADC: a sampling phase and a conversion phase. During the sampling phase, the SAR sub-ADC captures the analog input signal across multiple arrays of switchable capacitors. The conversion phase comprises a number of steps, and one or more bits of the digital output signal are resolved at each step of the conversion phase. A portion of the SC-DAC is driven by the delayed CT-SDADC output during the conversion phase to effectively compensate for excess loop delay caused by the CT-SDADC feedback loop.

Abstract translation: 本公开的CT-SDADC将模拟输入信号从模拟信号域中的表示转换为数字信号域中的表示以提供数字输出信号。 CT-SDADC通过在SAR子ADC中的两相之间切换实现模数转换和ELDC：采样阶段和转换阶段。 在采样阶段，SAR sub-ADC捕获多个可切换电容阵列上的模拟输入信号。 转换阶段包括多个步骤，并且数字输出信号的一个或多个位在转换阶段的每个步骤被​​解析。 在转换阶段，SC-DAC的一部分由延迟的CT-SDADC输出驱动，以有效地补偿由CT-SDADC反馈回路引起的多余的环路延迟。

公开(公告)号：US20160233872A1

公开(公告)日：2016-08-11

申请号：US14954532

申请日：2015-11-30

Applicant: BROADCOM CORPORATION

Inventor： Guowen WEI ,  Xinyu Yu ,  Michael Inerfield ,  Tom Kwan

IPC: H03M1/06 ,  H03M1/38 ,  H03M3/00

CPC classification number: H03M3/37 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/144 ,  H03M1/466 ,  H03M1/804 ,  H03M3/426

Abstract: A CT-SDADC of the present disclosure converts the analog input signal from a representation in an analog signal domain to a representation in a digital signal domain to provide the digital output signal. The CT-SDADC achieves the analog-to-digital conversion and ELDC by switching between two phases in the SAR sub-ADC: a sampling phase and a conversion phase. During the sampling phase, the SAR sub-ADC captures the analog input signal across multiple arrays of switchable capacitors. The conversion phase comprises a number of steps, and one or more bits of the digital output signal are resolved at each step of the conversion phase. A portion of the SC-DAC is driven by the delayed CT-SDADC output during the conversion phase to effectively compensate for excess loop delay caused by the CT-SDADC feedback loop.

Abstract translation: 本公开的CT-SDADC将模拟输入信号从模拟信号域中的表示转换为数字信号域中的表示以提供数字输出信号。 CT-SDADC通过在SAR子ADC中的两相之间切换实现模数转换和ELDC：采样阶段和转换阶段。 在采样阶段，SAR sub-ADC捕获多个可切换电容阵列上的模拟输入信号。 转换阶段包括多个步骤，并且数字输出信号的一个或多个位在转换阶段的每个步骤被​​解析。 在转换阶段，SC-DAC的一部分由延迟的CT-SDADC输出驱动，以有效地补偿由CT-SDADC反馈回路引起的多余的环路延迟。

公开(公告)号：US20140176359A1

公开(公告)日：2014-06-26

申请号：US13722388

申请日：2012-12-20

Applicant: BROADCOM CORPORATION

Inventor： Jason Hu ,  Xinyu Yu ,  Jing Yang ,  Sumant Ranganathan

IPC: H03M1/12

CPC classification number: H03M1/0845

Abstract: An analog-to-digital converter (ADC) includes reference charge cancellation features to at least partially offset a voltage distortion on a bypass capacitor of a reference buffer due to a voltage reference hit taken by a switched capacitor bank with which the bypass capacitor is connected. The charge cancellation may be configured in logic to be input signal dependent because different resolved bits or transitions between resolved bits may cause different amounts of voltage reference hits. By adjusting the bypass capacitor in response to each of at least some of the reference hits while resolving a word of bits, the reference voltage signal provided by the bypass capacitor undergoes far less settling, remaining more stable and linear for a more accurate reference voltage. Furthermore, a smaller capacitor may be used for the bypass capacitor, reducing power consumption and area on chip.

Abstract translation: 模数转换器（ADC）包括参考电荷消除特征，以至少部分地偏移参考缓冲器的旁路电容器上的电压失真，这是由于旁路电容器连接的开关电容器组所引起的电压基准点 。 电荷消除可以被配置为逻辑以输入信号，因为解析的位之间的不同的分辨位或转换可能导致不同量的电压参考点。 通过在解析位字时响应于至少一些参考命中中的每一个来调节旁路电容器，由旁路电容器提供的参考电压信号经历较少的稳定，对于更准确的参考电压，保持更稳定和线性。 此外，旁路电容器可以使用较小的电容器，从而降低功耗和芯片上的面积。