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公开(公告)号：US11295651B2
公开(公告)日：2022-04-05
申请号：US16939188
申请日：2020-07-27
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Junrui Zhang , Xuehui Zhu , Lijia Zhou , Zhidong Wang , Quanguo Zhou , Yungchiang Lee , Meng Guo , Jiuyang Cheng , Zongze He , Qin Liu
Abstract: Counter, pixel circuit, display panel, display device are provided. The counter includes: start-up circuit generating and outputting start-up signal by clock signal; M first and M second combinational logic circuits, alternate and cascaded, where M is integer no less than 1. Input terminal of first combinational logic circuit is coupled to output terminal of start-up circuit or second combinational logic circuit of previous stage, input terminal of second combinational logic circuit is coupled to output terminal of first combinational logic circuit of previous stage. Clock signal terminals of first, second combinational logic circuits are for inputting clock signal. First combinational logic circuit is for outputting clock signal in first time period and continuously outputting low level signal in second time period. Second combinational logic circuit is for outputting inverted signal of clock signal in third time period and continuously outputting low level signal in fourth time period.
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公开(公告)号：US20210097914A1
公开(公告)日：2021-04-01
申请号：US16939188
申请日：2020-07-27
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Junrui Zhang , Xuehui Zhu , Lijia Zhou , Zhidong Wang , Quanguo Zhou , Yungchiang Lee , Meng Guo , Jiuyang Cheng , Zongze He , Qin Liu
Abstract: Counter, pixel circuit, display panel, display device are provided. The counter includes: start-up circuit generating and outputting start-up signal by clock signal; M first and M second combinational logic circuits, alternate and cascaded, where M is integer no less than 1. Input terminal of first combinational logic circuit is coupled to output terminal of start-up circuit or second combinational logic circuit of previous stage, input terminal of second combinational logic circuit is coupled to output terminal of first combinational logic circuit of previous stage. Clock signal terminals of first, second combinational logic circuits are for inputting clock signal. First combinational logic circuit is for outputting clock signal in first time period and continuously outputting low level signal in second time period. Second combinational logic circuit is for outputting inverted signal of clock signal in third time period and continuously outputting low level signal in fourth time period.
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公开(公告)号：US11790188B2
公开(公告)日：2023-10-17
申请号：US17106683
申请日：2020-11-30
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jiuyang Cheng , Hao Tang , Quanguo Zhou , Qin Liu , Lirong Xu , Lijia Zhou
CPC classification number: G06K7/10099 , G06K7/10366 , G06Q10/08
Abstract: A positioning method performed at a server includes: receiving, at a frequency, arrival time information from a plurality of readers; determining, according to the arrival time information, that the tag is in a sensing auxiliary region of a positioning region; sending a first control command to one of the readers, so that the tag activates an inertial sensor thereof according to the first control command; receiving, from the reader, position information of the tag in the sensing auxiliary region obtained by the inertial sensor; determining, according to the position information of the tag in the sensing auxiliary region, a first motion trajectory of the tag in the sensing auxiliary region; and determining, according to the first motion trajectory, whether the tag enters one of the first regions.
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