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公开(公告)号：US20180032336A1
公开(公告)日：2018-02-01
申请号：US15279217
申请日：2016-09-28
Inventor： Wei QI , Jian OUYANG , Yong WANG
IPC: G06F9/30 , G06F12/0875
CPC classification number: G06F9/30043 , G06F9/3877 , G06F12/0875 , G06F2212/452
Abstract: The present application discloses a processor and a method for executing an instruction on a processor. A specific implementation of the processor includes: a host interaction device, an instruction control device, an off-chip memory, an on-chip cache and an array processing device, wherein the host interaction device is configured to exchange data and instructions with a host connected with the processor, wherein the exchanged data has a granularity of a matrix; the off-chip memory is configured to store a matrix received from the host, on which a matrix operation is to be performed; and the instruction control device is configured to convert an external instruction received from the host to a series of memory access instructions and a series of computing instructions and execute the converted instructions. The implementation can improve the execution efficiency of a deep learning algorithm.
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Patent Agency Ranking
2.发明申请公开(公告)号：US20190114202A1
公开(公告)日：2019-04-18
申请号：US16159322
申请日：2018-10-12
Inventor： Yong WANG , Jian OUYANG , Wei QI
Abstract: The present disclosure provides a task scheduling method and apparatus of artificial intelligence heterogeneous hardware, a device and a readable medium. The method comprises: receiving a task execution request for a corresponding function sent from an API, the task execution request carrying attribute information of the task; obtaining a priority of the task according to attribute information of the task, wherein a priority of an online service is higher than a priority of an offline task; inserting the corresponding task into a scheduling queue of a corresponding function according to the priority of the task; tasks in the scheduling queue being arranged in a descending order of priorities; controlling in turn a free computing unit in a plurality of computing units of the corresponding function to execute the corresponding task, in the descending order of priorities of the task in the scheduling queue. According to the technical solution of the present embodiment, it is feasible to achieve mixed performance of the offline model training task and online reasoning service according to the difference of priorities, thereby substantially improving the resource utilization rate.
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公开(公告)号：US20180123792A1
公开(公告)日：2018-05-03
申请号：US15619151
申请日：2017-06-09
CPC classification number: H04L9/30 , G09C1/00 , H04L9/06 , H04L9/0618 , H04L9/302 , H04L2209/12
Abstract: The present application discloses an RSA decryption processor and a method for controlling an RSA decryption processor. A specific implementation of the processor includes a memory, a control component, and a parallel processor. The memory is configured to store decryption parameters comprising a private key. The control component is configured to receive a ciphertext set, and send a decryption signal comprising the ciphertext set to the parallel processor. The parallel processor is configured to: read a decryption parameter from the memory in response to receiving the decryption signal, and use at least one modular exponentiation circuit unit in the parallel processor to perform in parallel a modular exponentiation operation on ciphertexts in the ciphertext set by using the read decryption parameter, to obtain plaintexts corresponding to the ciphertexts. This implementation improves the efficiency of RSA decryption.
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公开(公告)号：US20210034517A1
公开(公告)日：2021-02-04
申请号：US16942434
申请日：2020-07-29
Inventor： Xianglun LENG , Yong WANG , Wei QI , Zhengze QIU , Yang YAN
IPC: G06F12/02 , G06F12/1045 , G06F7/72
Abstract: Example embodiments of the present disclosure provide a method, an apparatus, a device and a computer-readable storage medium for storage management. The method for storage management includes: obtaining an available channel mode of a plurality of channels in a memory of a data processing system, the available channel mode indicating availabilities of the plurality of channels, and each of the plurality of channels being associated with a set of addresses in the memory; obtaining a channel data-granularity of the plurality of channels, the channel data-granularity indicating a size of a data block that can be carried on each channel; obtaining a target address of data to be transmitted in the memory; and determining a translated address corresponding to the target address based on the available channel mode and the channel data-granularity.
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公开(公告)号：US20180124023A1
公开(公告)日：2018-05-03
申请号：US15618655
申请日：2017-06-09
Inventor： Wei QI , Jian OUYANG , Yong WANG , Yichen TU , Sijie YANG
CPC classification number: H04L63/0435 , H04L9/006 , H04L9/0618 , H04L9/3271 , H04L63/0442 , H04L63/061 , H04L63/168 , H04L67/02
Abstract: The present application discloses a method, system and apparatus for storing a website private key plaintext. A specific implementation of the method includes: receiving a public key sent from a terminal configured to perform encryption and decryption, wherein the public key is generated at random by the terminal; encrypting a website private key plaintext by using the public key to generate a website private key ciphertext, wherein the website private key plaintext is pre-acquired; and sending the website private key ciphertext to the terminal, so that the terminal decrypts the website private key ciphertext by using the private key to generate the website private key plaintext and store the website private key plaintext in the terminal. This implementation improves the security of storage of the website private key plaintext.
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公开(公告)号：US20180121789A1
公开(公告)日：2018-05-03
申请号：US15618817
申请日：2017-06-09
Inventor： Jian OUYANG , Wei QI , Yong WANG , Lin LIU
CPC classification number: G06N3/04 , G06F5/012 , G06F7/483 , G06N3/0454 , G06N3/063
Abstract: The present application discloses a data processing method and apparatus. A specific implementation of the method includes: receiving floating point data sent from an electronic device; converting the received floating point data into fixed point data according to a data length and a value range of the received floating point data; performing calculation on the obtained fixed point data according to a preset algorithm to obtain result data in a fixed point form; and converting the obtained result data in the fixed point form into result data in a floating point form and sending the result data in the floating point form to the electronic device. This implementation improves the data processing efficiency.
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