公开(公告)号：US20140258956A1

公开(公告)日：2014-09-11

申请号：US14281735

申请日：2014-05-19

Applicant: Altera Corporation

Inventor： David Lewis ,  Christopher Lane ,  Sarathy Partha Sribhashyam ,  Srinivas Perisetty ,  Tim Vanderhoek ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy L. Lee

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  H03K19/17784

Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Abstract translation: 可编程逻辑器件（PLD）包括非易失性存储器，配置存储器和控制电路。 控制电路耦合到非易失性存储器和配置存储器。 一组电压从控制电路的输出导出，并被应用于PLD内的电路。

公开(公告)号：US09100011B1

公开(公告)日：2015-08-04

申请号：US14594832

申请日：2015-01-12

Applicant: ALTERA CORPORATION

Inventor： David Lewis ,  Valavan Manohararajah ,  David Galloway ,  Tim Vanderhoek

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/0944

CPC classification number: H03K19/1737 ,  H03K19/0944

Abstract: One embodiment relates to a circuit for pipelined direct-drive routing, the circuit including a routing multiplexer, a flip-flop, and a mode multiplexer. The output of the routing multiplexer is coupled to an input of the mode multiplexer and to the flip-flop. The output of the flip-flop is connected to another input of the mode multiplexer. The flip-flop may be directly connected to the routing multiplexer and the mode multiplexer, or, in an alternate embodiment, the flip-flop may be a member of a pipeline register pool. Another embodiment relates to a circuit for pipelined direct-drive routing which uses a pulse latch. Other embodiments relate to method for pipelined direct-drive routing which includes a degree of logical separation between logic elements and flip-flop elements. Another embodiment relates to a logic array block. Other embodiments, aspects, and features are also disclosed.

公开(公告)号：US08963581B1

公开(公告)日：2015-02-24

申请号：US13630925

申请日：2012-09-28

Applicant: Altera Corporation

Inventor： David Lewis ,  Valavan Manohararajah ,  David Galloway ,  Tim Vanderhoek

IPC: H03K19/177 ,  H03K19/173

CPC classification number: H03K19/1737 ,  H03K19/0944

Abstract: One embodiment relates to a circuit for pipelined direct-drive routing, the circuit including a routing multiplexer, a flip-flop, and a mode multiplexer. The output of the routing multiplexer is coupled to an input of the mode multiplexer and to the flip-flop. The output of the flip-flop is connected to another input of the mode multiplexer. The flip-flop may be directly connected to the routing multiplexer and the mode multiplexer, or, in an alternate embodiment, the flip-flop may be a member of a pipeline register pool. Another embodiment relates to a circuit for pipelined direct-drive routing which uses a pulse latch. Other embodiments relate to method for pipelined direct-drive routing which includes a degree of logical separation between logic elements and flip-flop elements. Another embodiment relates to a logic array block. Other embodiments, aspects, and features are also disclosed.

Abstract translation: 一个实施例涉及用于流水线直接驱动路由的电路，该电路包括路由多路复用器，触发器和模式多路复用器。 路由多路复用器的输出耦合到模式多路复用器和触发器的输入。 触发器的输出连接到模式多路复用器的另一输入端。 触发器可以直接连接到路由复用器和模式多路复用器，或者在替代实施例中，触发器可以是流水线寄存器池的成员。 另一实施例涉及使用脉冲锁存器的用于流水线直接驱动路由的电路。 其他实施例涉及用于流水线直接驱动路由的方法，其包括逻辑元件和触发器元件之间的逻辑间隔的程度。 另一实施例涉及逻辑阵列块。 还公开了其它实施例，方面和特征。