公开(公告)号：US09401718B1

公开(公告)日：2016-07-26

申请号：US14681419

申请日：2015-04-08

Applicant: Altera Corporation

Inventor： David Lewis ,  Valavan Manohararajah ,  David Galloway

IPC: H03K19/177

CPC classification number: H03K19/177 ,  G06F17/5054 ,  H01L25/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.

公开(公告)号：US09100011B1

公开(公告)日：2015-08-04

申请号：US14594832

申请日：2015-01-12

Applicant: ALTERA CORPORATION

Inventor： David Lewis ,  Valavan Manohararajah ,  David Galloway ,  Tim Vanderhoek

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/0944

CPC classification number: H03K19/1737 ,  H03K19/0944

Abstract: One embodiment relates to a circuit for pipelined direct-drive routing, the circuit including a routing multiplexer, a flip-flop, and a mode multiplexer. The output of the routing multiplexer is coupled to an input of the mode multiplexer and to the flip-flop. The output of the flip-flop is connected to another input of the mode multiplexer. The flip-flop may be directly connected to the routing multiplexer and the mode multiplexer, or, in an alternate embodiment, the flip-flop may be a member of a pipeline register pool. Another embodiment relates to a circuit for pipelined direct-drive routing which uses a pulse latch. Other embodiments relate to method for pipelined direct-drive routing which includes a degree of logical separation between logic elements and flip-flop elements. Another embodiment relates to a logic array block. Other embodiments, aspects, and features are also disclosed.

公开(公告)号：US08963581B1

公开(公告)日：2015-02-24

申请号：US13630925

申请日：2012-09-28

Applicant: Altera Corporation

Inventor： David Lewis ,  Valavan Manohararajah ,  David Galloway ,  Tim Vanderhoek

IPC: H03K19/177 ,  H03K19/173

CPC classification number: H03K19/1737 ,  H03K19/0944

Abstract: One embodiment relates to a circuit for pipelined direct-drive routing, the circuit including a routing multiplexer, a flip-flop, and a mode multiplexer. The output of the routing multiplexer is coupled to an input of the mode multiplexer and to the flip-flop. The output of the flip-flop is connected to another input of the mode multiplexer. The flip-flop may be directly connected to the routing multiplexer and the mode multiplexer, or, in an alternate embodiment, the flip-flop may be a member of a pipeline register pool. Another embodiment relates to a circuit for pipelined direct-drive routing which uses a pulse latch. Other embodiments relate to method for pipelined direct-drive routing which includes a degree of logical separation between logic elements and flip-flop elements. Another embodiment relates to a logic array block. Other embodiments, aspects, and features are also disclosed.

Abstract translation: 一个实施例涉及用于流水线直接驱动路由的电路，该电路包括路由多路复用器，触发器和模式多路复用器。 路由多路复用器的输出耦合到模式多路复用器和触发器的输入。 触发器的输出连接到模式多路复用器的另一输入端。 触发器可以直接连接到路由复用器和模式多路复用器，或者在替代实施例中，触发器可以是流水线寄存器池的成员。 另一实施例涉及使用脉冲锁存器的用于流水线直接驱动路由的电路。 其他实施例涉及用于流水线直接驱动路由的方法，其包括逻辑元件和触发器元件之间的逻辑间隔的程度。 另一实施例涉及逻辑阵列块。 还公开了其它实施例，方面和特征。

公开(公告)号：US08896344B1

公开(公告)日：2014-11-25

申请号：US13733985

申请日：2013-01-04

Applicant: Altera Corporation

Inventor： David Lewis ,  Valavan Manohararajah ,  David Galloway

IPC: H03K19/173 ,  G06F17/50 ,  H03K19/177

CPC classification number: H03K19/177 ,  G06F17/5054 ,  H01L25/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.

Abstract translation: 配置具有用户逻辑设计的可编程集成电路设备的方法包括分析用户逻辑设计以识别用户逻辑设计内的用户逻辑设计中的单向逻辑路径和在用户逻辑设计内的循环逻辑路径，将循环逻辑路径分配给第一 可编程集成电路器件以第一数据速率工作的部分，将单向逻辑路径分配给可编程集成电路器件的第二部分中的逻辑，该第二部分以低于第一数据速率的第二数据速率工作;以及流水线化单向 可编程集成电路器件的第二部分中的数据路径，以补偿较低的第二数据速率。 适于执行这种方法的可编程集成电路设备可以具有以不同速率操作的逻辑区域，包括具有可编程选择的数据速率的逻辑区域。

公开(公告)号：US08645885B1

公开(公告)日：2014-02-04

申请号：US13733994

申请日：2013-01-04

Applicant: Altera Corporation

Inventor： Valavan Manohararajah ,  David Galloway ,  David Lewis

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes accepting a first user input defining the user logic design, accepting a second user input defining multithreading characteristics of at least a portion the user logic design, determining a configuration of the programmable integrated circuit device having the user logic design, multithreading the at least a portion of the configuration based on the second user input, and retiming the multithreaded configuration.

Abstract translation: 配置具有用户逻辑设计的可编程集成电路器件的方法包括接受定义用户逻辑设计的第一用户输入，接受定义用户逻辑设计的至少一部分的多线程特性的第二用户输入，确定可编程 具有用户逻辑设计的集成电路设备，基于第二用户输入多线程配置的至少一部分，以及重新定时多线程配置。

公开(公告)号：US20160239043A1

公开(公告)日：2016-08-18

申请号：US15141201

申请日：2016-04-28

Applicant: Altera Corporation

Inventor： David Galloway ,  David Lewis ,  Ryan Fung ,  Valavan Manohararajah ,  Jeffrey Christopher Chromczak

IPC: G06F1/10 ,  G06F13/40

CPC classification number: G06F1/10 ,  G06F1/08 ,  G06F13/4068

Abstract: An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.

公开(公告)号：US09030231B1

公开(公告)日：2015-05-12

申请号：US14455014

申请日：2014-08-08

Applicant: Altera Corporation

Inventor： David Lewis ,  Valavan Manohararajah ,  David Galloway

IPC: H01L25/00 ,  H03K19/00 ,  G06F17/50 ,  H03K19/177

CPC classification number: H03K19/177 ,  G06F17/5054 ,  H01L25/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.

Abstract translation: 配置具有用户逻辑设计的可编程集成电路设备的方法包括分析用户逻辑设计以识别用户逻辑设计内的用户逻辑设计中的单向逻辑路径和在用户逻辑设计内的循环逻辑路径，将循环逻辑路径分配给第一 可编程集成电路器件以第一数据速率工作的部分，将单向逻辑路径分配给可编程集成电路器件的第二部分中的逻辑，该第二部分以低于第一数据速率的第二数据速率工作;以及流水线化单向 可编程集成电路器件的第二部分中的数据路径，以补偿较低的第二数据速率。 适于执行这种方法的可编程集成电路设备可以具有以不同速率操作的逻辑区域，包括具有可编程选择的数据速率的逻辑区域。

公开(公告)号：US09360884B2

公开(公告)日：2016-06-07

申请号：US14075802

申请日：2013-11-08

Applicant: Altera Corporation

Inventor： David Galloway ,  David Lewis ,  Ryan Fung ,  Valavan Manohararajah ,  Jeffrey Christopher Chromczak

IPC: G06F13/34 ,  G06F1/10 ,  G06F1/08

CPC classification number: G06F1/10 ,  G06F1/08 ,  G06F13/4068

Abstract: An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.

Abstract translation: 集成电路可以具有流水线可编程互连，其被配置为在存储在寄存器中的路由信号与绕过寄存器的相同路由信号之间进行选择。 流水线可编程互连可以通过线将所选择的路由信号发送到下一个流水线可编程互连电路。 集成电路还可以具有时钟路由选择电路，以选择用于不同流水线可编程互连中的寄存器的相应时钟信号。 时钟路由电路可以包括传送区域时钟的第一互连，传送路由时钟的第二互连，第一选择器电路，以选择区域时钟之间的路由时钟;以及第二选择器电路，以选择各个寄存器的路由时钟。

公开(公告)号：US09124271B1

公开(公告)日：2015-09-01

申请号：US13765930

申请日：2013-02-13

Applicant: Altera Corporation

Inventor： Ryan Fung ,  David Galloway

IPC: G06F17/50 ,  H03K19/173

CPC classification number: H03K19/173 ,  G06F17/50 ,  G06F17/5031 ,  G06F17/505 ,  G06F2217/62

Abstract: A logic device includes a low-skew network that feeds a subset of elements on the logic device. The low-skew network includes a selector that can select from a plurality of signal sources which includes a first signal source and a second signal source, wherein the second signal source can reach at least one element outside of the subset.

Abstract translation: 逻辑设备包括在逻辑设备上馈送元素的子集的低偏移网络。 低偏移网络包括可以从包括第一信号源和第二信号源的多个信号源中选择的选择器，其中第二信号源可以到达子集外部的至少一个元件。

公开(公告)号：US08839172B1

公开(公告)日：2014-09-16

申请号：US14197770

申请日：2014-03-05

Applicant: Altera Corporation

Inventor： Valavan Manohararajah ,  David Galloway ,  David Lewis

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5081 ,  G06F17/5027 ,  G06F17/5031 ,  G06F2217/84

Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes accepting a first user input defining the user logic design, accepting a second user input defining latency characteristics of the user logic design, determining a configuration of the programmable integrated circuit device having the user logic design, and retiming the configuration based on the second user input.