公开(公告)号：US10311196B1

公开(公告)日：2019-06-04

申请号：US15043432

申请日：2016-02-12

Applicant: Altera Corporation

Inventor： David Lewis

IPC: G06F17/50

Abstract: A method for designing a system on a target device includes placing the system on the target device. Timing analysis is performed on the placed system to model delays by using a plurality of localized functions that overlap.

公开(公告)号：US10141936B2

公开(公告)日：2018-11-27

申请号：US15630436

申请日：2017-06-22

Applicant: Altera Corporation

Inventor： David Lewis ,  Herman Henry Schmit ,  Carl Ebeling

IPC: H03K19/0175 ,  H03K19/173 ,  H03K19/0185

Abstract: An integrated circuit may have pipelined interconnects that are configurable to operate in registered single data rate mode, registered double data rate mode, or in combinational mode. The pipelined interconnect may include routing multiplexers for selecting incoming signals, circuitry for serialization and de-serialization, and memory elements that are configurable to store one or two signals per clock period. Operating the pipeline interconnects in double data rate mode may provide a trade-off between reducing the number of physical wires that are required to implement a design at a constant bandwidth or increasing the bandwidth while keeping the number of physical wires constant.

公开(公告)号：US20170322775A1

公开(公告)日：2017-11-09

申请号：US15601779

申请日：2017-05-22

Applicant: Altera Corporation

Inventor： Ketan Padalia ,  David Cashman ,  David Lewis ,  Andy L. Lee ,  Jay Schleicher ,  Jinyong Yuan ,  Henry Kim

IPC: G06F7/575 ,  H03K19/177

CPC classification number: G06F7/575 ,  H03K19/177 ,  H03K19/17728

Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT's can perform arithmetic efficiently, as well as non-arithmetic functions.

公开(公告)号：US09432023B2

公开(公告)日：2016-08-30

申请号：US14886777

申请日：2015-10-19

Applicant: Altera Corporation

Inventor： David Lewis

IPC: H03K19/177 ,  G01R21/133 ,  G11C13/00

CPC classification number: H03K19/1732 ,  G01R21/133 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2213/77 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776

Abstract: Various structures and methods are disclosed related to routing and programming circuitry on integrated circuits (“IC”) that have arrays of programmable resistive switches. In some embodiments, routing structures utilize densely populated resistive switch arrays to provide for efficient selection circuits that route into and out of logic regions. In other embodiments, programming circuitry is provided to help maintain relatively consistent programming current throughout an array of resistive switches to be programmed. In other embodiments, methods are provided for programming resistive switches without violating given power constraints. These and other embodiments are described further herein.

公开(公告)号：US09401718B1

公开(公告)日：2016-07-26

申请号：US14681419

申请日：2015-04-08

Applicant: Altera Corporation

Inventor： David Lewis ,  Valavan Manohararajah ,  David Galloway

IPC: H03K19/177

CPC classification number: H03K19/177 ,  G06F17/5054 ,  H01L25/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.

公开(公告)号：US09298211B2

公开(公告)日：2016-03-29

申请号：US14332006

申请日：2014-07-15

Applicant: Altera Corporation

Inventor： David Lewis

IPC: G06F1/12 ,  G06F1/04 ,  G11C7/10

CPC classification number: G06F1/04 ,  G06F1/12 ,  G11C7/1075

Abstract: Integrated circuits having single-port memory elements may be provided. The single-port memory elements may be controlled using a control circuit to emulate multiport functionality. In one suitable embodiment, the control circuit may be an arbitration circuit configured to execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed. In another suitable embodiment, the control circuit may be a sequencing circuit configured to service memory access requests from a synchronous port and an asynchronous port. Memory access requests received at the synchronous port may be serviced immediately, whereas memory access requests received at the asynchronous port may be synchronized to an internal memory clock signal and may be serviced after a preceding memory access request associated with the synchronous port has been serviced.

Abstract translation: 可以提供具有单端口存储元件的集成电路。 可以使用控制电路来控制单端口存储器元件来模拟多端口功能。 在一个合适的实施例中，控制电路可以是被配置为一旦被仲裁电路接收到就执行存储器请求的仲裁电路。 正在执行当前存储器访问时接收的请求可以被保持，直到当前存储器访问已经完成。 在另一个合适的实施例中，控制电路可以是被配置为从同步端口和异步端口服务存储器访问请求的排序电路。 在同步端口处接收到的存储器访问请求可以立即被服务，而在异步端口处接收的存储器访问请求可以被同步到内部存储器时钟信号，并且可以在与同步端口相关联的先前的存储器访问请求被服务之后进行服务。

公开(公告)号：US20160043724A1

公开(公告)日：2016-02-11

申请号：US14886777

申请日：2015-10-19

Applicant: ALTERA CORPORATION

Inventor： David Lewis

IPC: H03K19/177 ,  G01R21/133

CPC classification number: H03K19/1732 ,  G01R21/133 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2213/77 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776

Abstract: Various structures and methods are disclosed related to routing and programming circuitry on integrated circuits (“IC”) that have arrays of programmable resistive switches. In some embodiments, routing structures utilize densely populated resistive switch arrays to provide for efficient selection circuits that route into and out of logic regions. In other embodiments, programming circuitry is provided to help maintain relatively consistent programming current throughout an array of resistive switches to be programmed. In other embodiments, methods are provided for programming resistive switches without violating given power constraints. These and other embodiments are described further herein.

Abstract translation: 公开了与具有可编程电阻开关阵列的集成电路（“IC”）上的布线和编程电路相关的各种结构和方法。 在一些实施例中，路由结构利用密集填充的电阻式开关阵列来提供路由进出逻辑区域的有效选择电路。 在其他实施例中，提供编程电路以帮助维持编程的整个电阻式开关阵列中的相对一致的编程电流。 在其他实施例中，提供了用于编程电阻式开关的方法，而不违反给定的功率约束。 这些和其他实施例在本文进一步描述。

公开(公告)号：US20150033198A1

公开(公告)日：2015-01-29

申请号：US14484655

申请日：2014-09-12

Applicant: Altera Corporation

Inventor： Ryan Fung ,  David Lewis ,  Valavan Manohararajah

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/50 ,  G06F17/5045 ,  G06F17/5059 ,  G06F17/5077 ,  G06F2217/84 ,  H03K19/17728 ,  H03K19/17736

Abstract: A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify timing requirements of paths within the user logic design, determining latency requirements along those paths, routing the user logic design based on availability of storage elements for incorporation into those paths to satisfy the latency requirements, and retiming the user logic design following that routing by incorporating at least some of the storage elements.

Abstract translation: 配置具有用户逻辑设计的集成电路设备的方法包括分析用户逻辑设计以识别用户逻辑设计内的路径的定时要求，确定沿着这些路径的等待时间要求，基于存储元件的可用性路由用户逻辑设计， 并入到这些路径中以满足等待时间要求，并且通过并入至少一些存储元件来重新定时跟踪该路由之后的用户逻辑设计。

公开(公告)号：US08832627B1

公开(公告)日：2014-09-09

申请号：US14010356

申请日：2013-08-26

Applicant: Altera Corporation

Inventor： Mark Bourgeault ,  Ryan Fung ,  David Lewis

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/84 ,  H03K19/00323 ,  H03K19/17736

Abstract: An electronic design automation (EDA) tool alters a user's netlist to provide timing success for distribution of asynchronous signals. Distribution networks are used with the addition of pipeline registers before and/or after the distribution buffer. Or, a tree of pipeline registers is inserted between the asynchronous source and the destination registers. Or, any number of distribution networks are stitched together and pipeline stages may be inserted before and/or after each distribution buffer. Or, beneficial skew is utilized by introducing a delay component that skews a clock signal. The skewed clock signal drives a pipeline register that is inserted before a distribution buffer in order to improve timing margin. Any of various compilation techniques may be used within the EDA tool to solve the problem of distributing high-speed, high-fanout asynchronous signals. The technique has utility for high-performance FPGAs and structured ASIC families, as well as for low-cost FPGAs and other types of logic devices.

Abstract translation: 电子设计自动化（EDA）工具改变用户的网表以提供异步信号分配的时序成功。 分配网络在分配缓冲区之前和/或之后添加流水线寄存器时使用。 或者，在异步源和目标寄存器之间插入一条流水线寄存器树。 或者，任何数量的分发网络被缝合在一起，并且可以在每个分发缓冲器之前和/或之后插入流水线阶段。 或者，通过引入偏移时钟信号的延迟分量来利用有益的偏移。 偏斜时钟信号驱动在分配缓冲器之前插入的流水线寄存器，以便提高定时裕度。 可以在EDA工具中使用各种编译技术中的任何一种来解决分配高速，高扇出异步信号的问题。 该技术可用于高性能FPGA和结构化ASIC系列，以及低成本FPGA和其他类型的逻辑器件。

公开(公告)号：US10452392B1

公开(公告)日：2019-10-22

申请号：US14600322

申请日：2015-01-20

Applicant: Altera Corporation

Inventor： David Lewis ,  Valavan Manohararajah

IPC: G06F9/30

Abstract: A programmable integrated circuit device includes a plurality of clusters of programmable logic resources. Programmable device interconnect resources allow user-defined interconnection between the clusters of programmable logic resources. A plurality of specialized processing blocks have dedicated arithmetic operators and programmable internal interconnect resources, and having inputs and outputs programmably connectable to the programmable device interconnect resources. A plurality of embedded memory modules have inputs and outputs programmably connectable to the programmable device interconnect resources. Instruction sequencing circuitry is provided, and the instruction sequencing circuitry, at least one of the specialized processing blocks and at least one of the embedded memory modules, are programmably connectable to form a processor, where the memory module serves as instruction memory. Optionally, a dedicated instruction bus communicates the instructions from the embedded memory module or modules to the specialized processing block or blocks.