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公开(公告)号：US09660630B1
公开(公告)日：2017-05-23
申请号：US15295918
申请日：2016-10-17
Applicant: Altera Corporation
Inventor： Ramanand Venkata , Dana How , Christopher Lane
CPC classification number: H03L7/0807 , G06F1/10 , H03K3/01 , H03K5/159 , H03K19/1774 , H03K2005/00019 , H03L7/0812
Abstract: Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one ore more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.
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Patent Agency Ranking
公开(公告)号：US20140258956A1
公开(公告)日：2014-09-11
申请号：US14281735
申请日：2014-05-19
Applicant: Altera Corporation
Inventor： David Lewis , Christopher Lane , Sarathy Partha Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Yau-Tsun Wong , Andy L. Lee
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5077 , H03K19/17784
Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.
Abstract translation: 可编程逻辑器件（PLD）包括非易失性存储器，配置存储器和控制电路。 控制电路耦合到非易失性存储器和配置存储器。 一组电压从控制电路的输出导出，并被应用于PLD内的电路。
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公开(公告)号：US09843332B1
公开(公告)日：2017-12-12
申请号：US15496549
申请日：2017-04-25
Applicant: Altera Corporation
Inventor： Ramanand Venkata , Dana How , Christopher Lane
CPC classification number: H03L7/0807 , G06F1/10 , H03K3/01 , H03K5/159 , H03K19/1774 , H03K2005/00019 , H03L7/0812
Abstract: Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one or more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.
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公开(公告)号：US09473112B1
公开(公告)日：2016-10-18
申请号：US14137086
申请日：2013-12-20
Applicant: Altera Corporation
Inventor： Ramanand Venkata , Dana How , Christopher Lane
Abstract: Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one or more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.
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公开(公告)号：US20130214815A1
公开(公告)日：2013-08-22
申请号：US13847666
申请日：2013-03-20
Applicant: Altera Corporation
Inventor： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Christopher Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
IPC: H03K19/177
CPC classification number: H03K19/17736 , H03K19/177 , H03K19/17732 , H03K19/1778 , H03K19/17796
Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
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公开(公告)号：US09503057B1
公开(公告)日：2016-11-22
申请号：US14137086
申请日：2013-12-20
Applicant: Altera Corporation
Inventor： Ramanand Venkata , Dana How , Christopher Lane
CPC classification number: H03L7/0807 , G06F1/10 , H03K3/01 , H03K5/159 , H03K19/1774 , H03K2005/00019 , H03L7/0812
Abstract: Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one or more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.
Abstract translation: 系统和方法用于在集成电路上分配时钟或其他信号。 在一些方面，一个或多个分布式的偏移对象被配置用于减少或消除偏斜，同时将多个时钟分配段链接成任意形状和大小的一个时钟树。
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