-
1.发明授权Method for processing early arrival messages within a multinode asynchronous data communications system 失效在多节点异步数据通信系统中处理提前到达消息的方法
公开(公告)号：US5931915A
公开(公告)日：1999-08-03
申请号：US856619
申请日：1997-05-13
申请人： Alan F. Benner , Michael Grassi
发明人： Alan F. Benner , Michael Grassi
IPC分类号： H04L12/54 , G06F15/173 , G06F15/163
CPC分类号： G06F15/17368
摘要： A message-passing protocol for accommodating early arrival messages passed between source and destination nodes in a computer system with a plurality of asynchronous computing nodes interconnected by bidirectional asynchronous communications channels. The protocol includes transmitting the message from sender to receiver without waiting for a request for the message from the receiver; determining at the receiver if a receive buffer has been posted for the message; and if the receive buffer has not been posted for the message, then either truncating the message by storing its message header in an early arrival queue at the receiver and discarding its data or allocating a temporary receive buffer at the receiver to hold the message data. Upon the receiver being ready to post a receive buffer for an early arrival message, the receiver checks the early arrival queue for the corresponding message header, and if the message header is in the early arrival queue and the message data has been discarded, then the receiver sends a pull request to the sender to retransmit the message to the receiver.
摘要翻译： 一种消息传递协议，用于容纳在具有通过双向异步通信信道互连的多个异步计算节点的计算机系统中的源节点与目的节点之间传递的早到信息。 该协议包括从发送方发送消息到接收方，而不等待来自接收方的消息请求; 在接收器处确定是否已经为消息发布接收缓冲器; 并且如果接收缓冲器尚未被发送给消息，则通过将消息头部存储在接收器的早期到达队列中并且丢弃其数据或者在接收器处分配临时接收缓冲器来保存消息数据来截断该消息。 在接收器准备好发送用于早期到达消息的接收缓冲器的情况下，接收机检查相应消息报头的早期到达队列，并且如果消息报头处于早期到达队列中并且消息数据已被丢弃，则 接收方向发送方发送拉取请求，以将消息重发到接收方。
-
2.发明授权System for processing early arrival messages within a multinode asynchronous data communications system 失效用于在多节点异步数据通信系统内处理提前到达消息的系统
公开(公告)号：US5878226A
公开(公告)日：1999-03-02
申请号：US853701
申请日：1997-05-13
申请人： Alan F. Benner , Michael Grassi
发明人： Alan F. Benner , Michael Grassi
CPC分类号： G06F13/387
摘要： A message-passing protocol for accommodating early arrival messages passed between source and destination nodes in a computer system with a plurality of asynchronous computing nodes interconnected by bidirectional asynchronous communications channels. The protocol includes transmitting the message from sender to receiver without waiting for a request for the message from the receiver; determining at the receiver if a receive buffer has been posted for the message; and if the receive buffer has not been posted for the message, then either truncating the message by storing its message header in an early arrival queue at the receiver and discarding its data or allocating a temporary receive buffer at the receiver to hold the message data. Upon the receiver being ready to post a receive buffer for an early arrival message, the receiver checks the early arrival queue for the corresponding message header, and if the message header is in the early arrival queue and the message data has been discarded, then the receiver sends a pull request to the sender to retransmit the message to the receiver.
摘要翻译： 一种消息传递协议，用于容纳在具有通过双向异步通信信道互连的多个异步计算节点的计算机系统中的源节点与目的节点之间传递的早到信息。 该协议包括从发送方发送消息到接收方，而不等待来自接收方的消息请求; 在接收器处确定是否已经为消息发布接收缓冲器; 并且如果接收缓冲器尚未被发送给消息，则通过将消息头部存储在接收器的早期到达队列中并且丢弃其数据或者在接收器处分配临时接收缓冲器来保存消息数据来截断该消息。 在接收器准备好发送用于早期到达消息的接收缓冲器的情况下，接收机检查相应消息报头的早期到达队列，并且如果消息报头处于早期到达队列中并且消息数据已被丢弃，则 接收方向发送方发送拉取请求，以将消息重发到接收方。
-
公开(公告)号：US20210070392A1
公开(公告)日：2021-03-11
申请号：US16966447
申请日：2019-01-25
申请人： Michael Grassi
发明人： Michael Grassi
摘要： A shaft characterized by its length to diameter ratio being less than about 1.75 having a drive connection at one end where the wall thickness of the shaft is selected to be thick enough to avoid ellipticalization strain error in torsional measurement of less than 5%. One specific application is for a crankset spindle that can be used to measure a cyclist right, left, and total leg torque.
-
4.发明授权Memory controller having tables mapping memory addresses to memory modules 失效内存控制器具有将内存地址映射到内存模块的表格公开(公告)号：US08250330B2
公开(公告)日：2012-08-21
申请号：US11010205
申请日：2004-12-11
CPC分类号： G06F12/0653 , G06F13/1668
摘要： A memory controller includes ports and corresponding tables. Each port is receptive to one or more memory modules. Each table includes entries mapping memory addresses to the memory modules. Each entry corresponds to no more than one of the memory modules. The tables support asymmetric population of the memory modules within the ports; each port is capable of having a different number of memory modules relative to the other ports. The tables impose no restrictions on where the memory modules are to be inserted within the ports, both number-wise and position-wise. The tables are independently configurable; the configuration of each table is modifiable independently of the configurations of the other tables. Each table is dynamically configurable. The entries of a table are modifiable to reflect changes in the number and type of the memory modules connected, without restarting or temporarily halting the computer system containing the memory controller.
摘要翻译： 存储器控制器包括端口和对应的表。 每个端口都接受一个或多个内存模块。 每个表包括将内存地址映射到内存模块的条目。 每个条目对应于不超过一个内存模块。 这些表支持端口内存模块的非对称数量; 每个端口能够相对于其他端口具有不同数量的存储器模块。 这些表对数字和位置方面的内存模块在端口中插入的位置没有任何限制。 表可独立配置; 每个表的配置可以独立于其他表的配置进行修改。 每个表都是可动态配置的。 表的条目是可修改的，以反映连接的内存模块的数量和类型的变化，而不会重新启动或暂时中止包含内存控制器的计算机系统。
-
5.发明授权Data communication method and apparatus utilizing credit-based data transfer protocol and credit loss detection mechanism 失效数据通信方法和设备利用信用数据传输协议和信用损失检测机制公开(公告)号：US07647435B2
公开(公告)日：2010-01-12
申请号：US11761154
申请日：2007-06-11
CPC分类号： G06F13/36
摘要： A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver, the separate mechanism not necessarily being current. The local record is compared to the count of credits from the separate mechanism over a pre-determined time interval, failure of the two values to agree at any time during the interval indicating a probable credit discrepancy. A credit discrepancy is confirmed, preferably by suspending certain bus activity for a sufficiently long period to account for any delay in propagating credit value changes, and re-comparing the values. Preferably, the bus communicates between internal components of an integrated circuit chip.
摘要翻译： 用于数字设备的通信总线包括基于信用的流量控制机制，其中发送组件保持其信用的本地记录。 通过脉冲单位信用回报线将积分返还给发送方。 单独的机制提供来自接收器的可用信用的计数，单独的机制不一定是当前的。 将本地记录与预定时间间隔内的单独机制的信用计数进行比较，两个值在表示可能的信用差异的间隔期间的任何时间失败。 确认信用差异，最好是通过暂停一段长时间的公共汽车活动来解决传播信用额度变化的任何延误，并重新比较价值。 优选地，总线在集成电路芯片的内部部件之间进行通信。
-
6.发明授权Utilizing programmable channels for allocation of buffer space and transaction control in data communications 失效利用可编程通道在数据通信中分配缓冲区空间和事务控制公开(公告)号：US07882278B2
公开(公告)日：2011-02-01
申请号：US12362585
申请日：2009-01-30
IPC分类号： G06F13/42
CPC分类号： G06F13/4059
摘要： A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.
摘要翻译： 用于数据总线通信的控制机制采用分配总线事务的通道，每个通道具有独立的流量控制。 控制机制强制通道之间的排序算法，由此至少一些交易可以通过其他交易。 通道属性可编程以改变排序条件。 优选地，每个信道被分配其自己的可编程缓冲区。 控制机制为每个通道独立地确定缓冲区空间是否可用，并相应地为每个通道独立地执行流量控制。 流量控制优选地是基于信用的，表示缓冲区空间的信用或接收器接收数据的一些其他容量。 优选地，流量控制机构包括控制集成电路芯片的内部通信的中央互连模块。
-
7.发明申请Utilizing Programmable Channels for Allocation of Buffer Space and Transaction Control in Data Communications 失效利用可编程通道分配数据通信中的缓冲区空间和事务控制公开(公告)号：US20090138629A1
公开(公告)日：2009-05-28
申请号：US12362585
申请日：2009-01-30
IPC分类号： G06F13/42
CPC分类号： G06F13/4059
摘要： A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.
摘要翻译： 用于数据总线通信的控制机制采用分配总线事务的通道，每个通道具有独立的流量控制。 控制机制强制通道之间的排序算法，由此至少一些交易可以通过其他交易。 通道属性可编程以改变排序条件。 优选地，每个信道被分配其自己的可编程缓冲区。 控制机制为每个通道独立地确定缓冲区空间是否可用，并相应地为每个通道独立地执行流量控制。 流量控制优选地是基于信用的，表示缓冲区空间的信用或接收器接收数据的一些其他容量。 优选地，流量控制机构包括控制集成电路芯片的内部通信的中央互连模块。
-
8.发明授权Data communication method and apparatus utilizing programmable channels for allocation of buffer space and transaction control 失效数据通信方法和装置利用可编程通道分配缓冲区空间和事务控制公开(公告)号：US07493426B2
公开(公告)日：2009-02-17
申请号：US11047548
申请日：2005-01-31
IPC分类号： G06F3/00 , G06F5/00 , G06F11/00 , G01R31/08 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26
CPC分类号： G06F13/4059
摘要： A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.
摘要翻译： 用于数据总线通信的控制机制采用分配总线事务的通道，每个通道具有独立的流量控制。 控制机制强制通道之间的排序算法，由此至少一些交易可以通过其他交易。 通道属性可编程以改变排序条件。 优选地，每个信道被分配其自己的可编程缓冲区。 控制机制为每个通道独立地确定缓冲区空间是否可用，并相应地为每个通道独立地执行流量控制。 流量控制优选地是基于信用的，表示缓冲区空间的信用或接收器接收数据的一些其他容量。 优选地，流量控制机构包括控制集成电路芯片的内部通信的中央互连模块。
-
公开(公告)号：US20080238407A1
公开(公告)日：2008-10-02
申请号：US11694424
申请日：2007-03-30
申请人： Michael Grassi , Alex Levin , John Dickerson
发明人： Michael Grassi , Alex Levin , John Dickerson
IPC分类号： G01R1/02
CPC分类号： G06F1/26
摘要： A system and method for voltage sensing at active power gated cores of a multi core CPU wherein a Controlled Collapse Chip Carrier bump in a gating region for an associated core is isolatable from an ungated power region by a power gate to allow voltage sensing at a designated location with substantially no current passing there through.
摘要翻译： 一种用于多核CPU的有源电力门控核心处的电压感测的系统和方法，其中用于相关核的门控区域中的受控塌陷芯片载体凸块可通过功率门与非门控功率区域隔离，以允许在指定的 位置基本上没有电流通过。
-
10.发明申请Data Communication Method and Apparatus Utilizing Credit-Based Data Transfer Protocol and Credit Loss Detection Mechanism 失效数据通信方法与利用信用数据传输协议和信用损失检测机制的设备公开(公告)号：US20070233918A1
公开(公告)日：2007-10-04
申请号：US11761154
申请日：2007-06-11
申请人： Mark Check , Bernard Drerup , Michael Grassi
发明人： Mark Check , Bernard Drerup , Michael Grassi
IPC分类号： G06F13/00
CPC分类号： G06F13/36
摘要： A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver, the separate mechanism not necessarily being current. The local record is compared to the count of credits from the separate mechanism over a pre-determined time interval, failure of the two values to agree at any time during the interval indicating a probable credit discrepancy. A credit discrepancy is confirmed, preferably by suspending certain bus activity for a sufficiently long period to account for any delay in propagating credit value changes, and re-comparing the values. Preferably, the bus communicates between internal components of an integrated circuit chip
摘要翻译： 用于数字设备的通信总线包括基于信用的流量控制机制，其中发送组件保持其信用的本地记录。 通过脉冲单位信用回报线将积分返还给发件人。 单独的机制提供来自接收器的可用信用的计数，单独的机制不一定是当前的。 将本地记录与预定时间间隔内的单独机制的信用计数进行比较，两个值在表示可能的信用差异的间隔期间的任何时间失败。 确认信用差异，最好是通过暂停一段长时间的公共汽车活动来解决传播信用额度变化的任何延误，并重新比较价值。 优选地，总线在集成电路芯片的内部部件之间进行通信
-
-
-
-
-
-
-
-
-
搜索结果
22 条记录 (耗时 0.033 秒)
