公开(公告)号：US20220156345A1

公开(公告)日：2022-05-19

申请号：US17601778

申请日：2020-05-28

Applicant: Adesto Technologies Corporation

Inventor： John R. Jameson

IPC: G06F17/16 ,  G11C13/00

Abstract: A memory device includes a memory array arranged in rows and columns; memory cell layers at each row and column intersection, where each memory cell layer is configured to be set to a predetermined conductance state; a row control circuit that is configured to apply voltages to the rows by applying sub-voltages on each row, where each sub-voltage corresponds to a different memory cell layer, and where each sub-voltage is proportional to the voltage on the corresponding row; and a sensing circuit that is configured to determine a column current flowing through a selected column in response to the application of the voltages to the rows, where the column current is a sum of currents through each memory cell layer that corresponds to the selected column.

公开(公告)号：US11537754B1

公开(公告)日：2022-12-27

申请号：US16571051

申请日：2019-09-13

Applicant: Adesto Technologies Corporation

Inventor： John R. Jameson ,  David Kim ,  Foroozan Sarah Koushan

IPC: G06F21/75 ,  H04L9/32 ,  G06F21/72 ,  G11C13/00 ,  G06F7/58 ,  G11C11/16

Abstract: An integrated circuit device can include a plurality of nonvolatile memory elements having values that vary randomly or pseudo-randomly from one another; a selection circuit configured to select a plurality of nonvolatile memory elements that vary randomly or pseudo-randomly in response to a received challenge value; and sense circuits configured to generate a response value based on the values of the selected nonvolatile memory elements. Related methods and systems are also disclosed.

公开(公告)号：US09368206B1

公开(公告)日：2016-06-14

申请号：US14325119

申请日：2014-07-07

Applicant: Adesto Technologies Corporation

Inventor： John Dinh ,  Ming Sang Kwan ,  Venkatesh P. Gopinath ,  Derric Lewis ,  Shane Hollmer ,  John R. Jameson ,  Michael Van Buskirk

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/24 ,  G11C11/5614 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0097 ,  G11C2213/76 ,  G11C2213/78

Abstract: In one embodiment, a capacitive circuit can include: (i) a resistive storage element having a solid electrolyte, a first electrode coupled to a first side of the solid electrolyte, and a second electrode coupled to a second side of the solid electrolyte; (ii) the resistive storage element being configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction to form a conductive path between the first and second electrodes, and being configured to be erased to a high resistance state by application of an erase voltage in a reverse bias direction to substantially dissolve the conductive path; and (iii) a first capacitor having the first electrode coupled to a first side of a first oxide layer, and a third electrode coupled to a second side of the first oxide layer.

Abstract translation: 在一个实施例中，电容电路可以包括：（i）具有固体电解质的电阻存储元件，耦合到固体电解质的第一侧的第一电极和耦合到固体电解质的第二侧的第二电极; （ii）电阻存储元件被配置为通过在正向偏置方向上施加编程电压而被编程为低电阻状态，以在第一和第二电极之间形成导电路径，并且被配置为被擦除为高电阻 通过在反向偏置方向施加擦除电压以使导电路径基本上溶解; 和（iii）第一电容器，其具有耦合到第一氧化物层的第一侧的第一电极和耦合到第一氧化物层的第二侧的第三电极。