公开(公告)号：US11956019B1

公开(公告)日：2024-04-09

申请号：US17179527

申请日：2021-02-19

申请人： Acacia Communications, Inc.

发明人： Ramesh K. Singh ,  Ian Dedic ,  Gavin Allen

IPC分类号： H04B10/04 ,  H04B10/50 ,  H04B10/508 ,  H04B10/516

CPC分类号： H04B10/501 ,  H04B10/508 ,  H04B10/516

摘要： A method, system, and apparatus for multiplexing comprising feeding a signal into a sampler, splitting a first signal into an even branch at a first set of times, splitting a second signal into an odd branch at a second set of times, feeding a switch bleed current into the first branch at the second set of time and feeding the switch bleed current into the second branch at the first set of time.

公开(公告)号：US12107544B1

公开(公告)日：2024-10-01

申请号：US16685063

申请日：2019-11-15

申请人： Acacia Communications, Inc.

发明人： Ian Dedic ,  Gavin Allen ,  David Enright ,  Guojun Ren

IPC分类号： H01F27/28 ,  H03B5/12

CPC分类号： H03B5/1259 ,  H01F27/28 ,  H03B5/1268

摘要： An apparatus comprising two inductors; wherein the two inductors are layered on top of each other in different layers of metal of a circuit; wherein each inductor of the inductor has a set of turns; wherein the current path of the two inductors is in the same direction.

公开(公告)号：US11432056B1

公开(公告)日：2022-08-30

申请号：US16938721

申请日：2020-07-24

申请人： Acacia Communications, Inc.

发明人： Christopher Doerr ,  Benny Mikkelsen ,  Ian Dedic ,  John LoMedico ,  Song Jiang

IPC分类号： H04Q11/00 ,  G02B6/42 ,  H01L25/18 ,  H04B10/25

摘要： An apparatus and system, including a switch; and a set of tiles; wherein each of the set of tiles include a PIC die, a DSP die, a driver die, and a TIA die and methods thereto.

公开(公告)号：US12130656B1

公开(公告)日：2024-10-29

申请号：US18343841

申请日：2023-06-29

申请人： Acacia Communications, Inc.

发明人： Gavin Allen ,  Ian Dedic ,  Bo Yang ,  Taran Gupta

IPC分类号： G06F1/10 ,  H03K3/037

CPC分类号： G06F1/10 ,  H03K3/037

摘要： A method system, and apparatus for adjusting skew in a circuit comprising feeding an input clock into a first push-pull source follower stage, feeding an inverse of an input clock bar into a first CMOS inverter stage, creating an output clock based on an equal contribution of the input clock of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage, feeding the input clock bar into a first push-pull source follower stage, feeding an inverse of the input clock into a first CMOS inverter stage, and creating an output clock based on an equal contribution of the input clock bar of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage.

公开(公告)号：US11599140B1

公开(公告)日：2023-03-07

申请号：US16587191

申请日：2019-09-30

申请人： Acacia Communications, Inc.

发明人： Ian Dedic ,  David Enright ,  Tarun Gupta

IPC分类号： G06F1/12 ,  H01P3/06 ,  H03B5/08

摘要： In a first and second embodiment, an apparatus and system comprising a set of voltage controlled oscillators (VCOs); wherein each VCO of the set of VCOs has an LC tank; wherein each VCO of the set of VCOs is connected via a transmission line. In a third embodiment, a method comprising connecting each VCO in a set of VCOs by connecting each respective LC tank of each VCO of the set of VCOs with a transmission line.

公开(公告)号：US12041397B1

公开(公告)日：2024-07-16

申请号：US17896668

申请日：2022-08-26

申请人： Acacia Communications, Inc.

发明人： Christopher Doerr ,  Benny Mikkelsen ,  Ian Dedic ,  John LoMedico ,  Song Jiang

IPC分类号： H04Q11/00 ,  G02B6/42 ,  H01L25/18 ,  H04B10/25

CPC分类号： H04Q11/0005 ,  G02B6/421 ,  G02B6/4269 ,  G02B6/4292 ,  H01L25/18 ,  H04B10/25 ,  H04Q2011/0039

摘要： An apparatus and system, including a switch; and a set of tiles; wherein each of the set of tiles include a PIC die, a DSP die, a driver die, and a TIA die and methods thereto.

公开(公告)号：US11923910B1

公开(公告)日：2024-03-05

申请号：US17531733

申请日：2021-11-20

申请人： Acacia Communications, Inc.

发明人： Christian Rasmussen ,  Ian Dedic ,  Benny Mikkelsen

IPC分类号： H04B10/00 ,  H04B1/04 ,  H04B10/556 ,  H04B10/80 ,  H04J14/00

CPC分类号： H04B10/803 ,  H04B1/04 ,  H04B10/556 ,  H04B2001/0408

摘要： A CMOS integrated circuit comprising digital-to-analogue converters (DACs), analogue-to-digital converters (ADCs), a digital signal processor (DSP), on-chip switching, an on-chip processor; and logic enabling to receive data from data sources in a 5G network, combine the data from the data sources into a single data stream, encode the single data stream using the DSP, and cause the encoded single data stream to be transmitted to another device in the 5G network.

公开(公告)号：US11698658B1

公开(公告)日：2023-07-11

申请号：US17833306

申请日：2022-06-06

申请人： Acacia Communications, Inc.

发明人： Gavin Allen ,  Ian Dedic ,  Bo Yang ,  Tarun Gupta

IPC分类号： G06F1/10 ,  H03K3/037

CPC分类号： G06F1/10 ,  H03K3/037

摘要： A method system, and apparatus for adjusting skew in a circuit comprising feeding an input clock into a first push-pull source follower stage, feeding an inverse of an input clock bar into a first CMOS inverter stage, creating an output clock based on an equal contribution of the input clock of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage, feeding the input clock bar into a first push-pull source follower stage, feeding an inverse of the input clock into a first CMOS inverter stage, and creating an output clock based on an equal contribution of the input clock bar of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage.

公开(公告)号：US11543850B1

公开(公告)日：2023-01-03

申请号：US16777968

申请日：2020-01-31

申请人： Acacia Communications, Inc.

发明人： Ian Dedic ,  Gavin Allen ,  David Enright ,  Bo Yang ,  Tarun Gupta

IPC分类号： G06F1/08 ,  H03B5/12 ,  H03F3/50

摘要： An apparatus and system for a clock buffer. The clock buffer comprises a source follower, and the source follower comprises a voltage source and a resistor.