公开(公告)号：US20140284606A1

公开(公告)日：2014-09-25

申请号：US13905107

申请日：2013-05-29

Applicant: AU Optronics Corp.

Inventor： Ssu-Hui Lu ,  Ming-Hsien Lee

IPC: H01L21/30 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/78675 ,  H01L21/3003 ,  H01L27/1214 ,  H01L27/1248 ,  H01L27/127

Abstract: A method for fabricating a pixel structure includes the following steps. A patterned semiconductor layer, an insulation layer, and a patterned metal layer are formed on a substrate sequentially. A first inter-layer dielectric (ILD) layer is formed to cover the patterned metal layer. A low temperature annealing process is performed after forming the first ILD layer. A hydrogen plasma treatment process is performed after the low temperature annealing process. A second ILD layer is formed to cover the first ILD layer after the hydrogen plasma treatment process. A third ILD layer is formed to cover the second ILD layer. A source electrode and a drain electrode are formed on the third ILD layer. A passivation layer is formed on the source electrode and the drain electrode. A pixel electrode is formed on the passivation layer. A pixel structure manufactured by the above-mentioned method is also provided.

Abstract translation: 一种用于制造像素结构的方法包括以下步骤。 在基板上顺序地形成图案化的半导体层，绝缘层和图案化的金属层。 形成第一层间电介质层（ILD）以覆盖图案化的金属层。 在形成第一ILD层之后进行低温退火处理。 在低温退火处理之后进行氢等离子体处理。 在氢等离子体处理过程之后，形成第二ILD层以覆盖第一ILD层。 形成第三ILD层以覆盖第二ILD层。 源电极和漏电极形成在第三ILD层上。 在源电极和漏电极上形成钝化层。 在钝化层上形成像素电极。 还提供了通过上述方法制造的像素结构。

公开(公告)号：US20160299381A1

公开(公告)日：2016-10-13

申请号：US14880292

申请日：2015-10-12

Applicant: AU Optronics Corp.

Inventor： Ssu-Hui Lu ,  Ming-Hsien Lee

IPC: G02F1/1335 ,  G02F1/1362 ,  G02F1/139 ,  G02F1/1368 ,  G02F1/1343 ,  G02F1/1339

CPC classification number: G02F1/133555 ,  G02F1/133553 ,  G02F1/133602 ,  G02F1/134336 ,  G02F1/1393 ,  G02F2001/133391 ,  G02F2001/134372

Abstract: A liquid crystal display panel includes a first substrate, a second substrate, at least one liquid crystal layer, a first pixel array and a second pixel array. The liquid crystal layer is interposed between the first substrate and the second substrate. The first pixel array is disposed in a first display region of the first substrate, where the first pixel array includes a plurality of first transmissive sub-pixels arranged in columns and rows and disposed adjacent to each other. The second pixel array is disposed in a second display region of the first substrate, and the second pixel array includes a plurality of reflective sub-pixels arranged in columns and rows.

Abstract translation: 液晶显示面板包括第一基板，第二基板，至少一个液晶层，第一像素阵列和第二像素阵列。 液晶层介于第一基板和第二基板之间。 第一像素阵列设置在第一衬底的第一显示区域中，其中第一像素阵列包括以列和行排列并且彼此相邻布置的多个第一透射子像素。 第二像素阵列设置在第一衬底的第二显示区域中，并且第二像素阵列包括以列和行排列的多个反射子像素。

公开(公告)号：US08999775B2

公开(公告)日：2015-04-07

申请号：US13905107

申请日：2013-05-29

Applicant: AU Optronics Corp.

Inventor： Ssu-Hui Lu ,  Ming-Hsien Lee

IPC: H01L21/84 ,  H01L21/30 ,  H01L27/12

CPC classification number: H01L29/78675 ,  H01L21/3003 ,  H01L27/1214 ,  H01L27/1248 ,  H01L27/127

Abstract: A method for fabricating a pixel structure includes the following steps. A patterned semiconductor layer, an insulation layer, and a patterned metal layer are formed on a substrate sequentially. A first inter-layer dielectric (ILD) layer is formed to cover the patterned metal layer. A low temperature annealing process is performed after forming the first ILD layer. A hydrogen plasma treatment process is performed after the low temperature annealing process. A second ILD layer is formed to cover the first ILD layer after the hydrogen plasma treatment process. A third ILD layer is formed to cover the second ILD layer. A source electrode and a drain electrode are formed on the third ILD layer. A passivation layer is formed on the source electrode and the drain electrode. A pixel electrode is formed on the passivation layer. A pixel structure manufactured by the above-mentioned method is also provided.

Abstract translation: 一种用于制造像素结构的方法包括以下步骤。 在基板上顺序地形成图案化的半导体层，绝缘层和图案化的金属层。 形成第一层间电介质层（ILD）以覆盖图案化的金属层。 在形成第一ILD层之后进行低温退火处理。 在低温退火处理之后进行氢等离子体处理。 在氢等离子体处理过程之后，形成第二ILD层以覆盖第一ILD层。 形成第三ILD层以覆盖第二ILD层。 源电极和漏电极形成在第三ILD层上。 在源电极和漏电极上形成钝化层。 在钝化层上形成像素电极。 还提供了通过上述方法制造的像素结构。

公开(公告)号：US08865532B2

公开(公告)日：2014-10-21

申请号：US13625949

申请日：2012-09-25

Applicant: AU Optronics Corp.

Inventor： Jia-Hong Ye ,  Ssu-Hui Lu ,  Wu-Hsiung Lin ,  Chao-Chien Chiu ,  Ming-Hsien Lee ,  Chia-Tien Peng ,  Wei-Ming Huang

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L27/1255 ,  H01L27/1218 ,  H01L27/1248 ,  H01L29/78603

Abstract: A method for manufacturing an active device array substrate includes providing a flexible substrate having a transistor region and a transparent region; forming a gate electrode on the transistor region; sequentially forming a dielectric layer and a semiconductor layer to cover the gate electrode and the flexible substrate; removing a part of the semiconductor layer to form a channel layer above the gate electrode and removing a thickness of the dielectric layer disposed on the transparent region, such that a portion of the dielectric layer on the gate electrode has a first thickness, and another portion of the dielectric layer on the transparent region has a second thickness less than the first thickness; respectively forming a source electrode and a drain electrode on opposite sides of the channel layer; and forming a pixel electrode electrically connected to the drain electrode.

Abstract translation: 一种有源器件阵列衬底的制造方法，包括提供具有晶体管区域和透明区域的柔性衬底; 在晶体管区上形成栅电极; 顺序地形成介电层和半导体层以覆盖栅电极和柔性基板; 去除所述半导体层的一部分以在所述栅极电极上方形成沟道层，并且去除设置在所述透明区域上的所述电介质层的厚度，使得所述栅电极上的所述电介质层的一部分具有第一厚度， 在所述透明区域上的所述电介质层的厚度小于所述第一厚度的第二厚度; 分别在沟道层的相对侧上形成源电极和漏电极; 以及形成与漏电极电连接的像素电极。

公开(公告)号：US09224868B2

公开(公告)日：2015-12-29

申请号：US14622906

申请日：2015-02-15

Applicant: AU Optronics Corp.

Inventor： Ssu-Hui Lu ,  Ming-Hsien Lee

IPC: H01L29/786 ,  H01L21/30 ,  H01L27/12

CPC classification number: H01L29/78675 ,  H01L21/3003 ,  H01L27/1214 ,  H01L27/1248 ,  H01L27/127

Abstract: A pixel structure includes a substrate, a patterned semiconductor layer, an insulation layer, a gate electrode, a first inter-layer dielectric (ILD) layer, a second ILD layer, a third ILD layer, a source electrode and a drain electrode. The patterned semiconductor layer is disposed on the substrate. The insulation layer is disposed on the patterned semiconductor layer. The gate electrode is disposed on the insulation layer. The first ILD layer is disposed on the gate electrode, the second ILD layer is disposed on the first ILD layer, and the third ILD layer is disposed on the second ILD layer. The source electrode and the drain electrode are disposed on the third ILD layer, wherein the source electrode and the drain electrode are electrically connected to the patterned semiconductor layer via a first contact window and a second contact window respectively.

Abstract translation: 像素结构包括衬底，图案化半导体层，绝缘层，栅电极，第一层间电介质（ILD）层，第二ILD层，第三ILD层，源电极和漏电极。 图案化半导体层设置在基板上。 绝缘层设置在图案化的半导体层上。 栅电极设置在绝缘层上。 第一ILD层设置在栅电极上，第二ILD层设置在第一ILD层上，第三ILD层设置在第二ILD层上。 源电极和漏极设置在第三ILD层上，其中源电极和漏电极分别经由第一接触窗口和第二接触窗口电连接到图案化半导体层。

公开(公告)号：US20150162453A1

公开(公告)日：2015-06-11

申请号：US14622906

申请日：2015-02-15

Applicant: AU Optronics Corp.

Inventor： Ssu-Hui Lu ,  Ming-Hsien Lee

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78675 ,  H01L21/3003 ,  H01L27/1214 ,  H01L27/1248 ,  H01L27/127

Abstract: A pixel structure includes a substrate, a patterned semiconductor layer, an insulation layer, a gate electrode, a first inter-layer dielectric (ILD) layer, a second ILD layer, a third ILD layer, a source electrode and a drain electrode. The patterned semiconductor layer is disposed on the substrate. The insulation layer is disposed on the patterned semiconductor layer. The gate electrode is disposed on the insulation layer. The first ILD layer is disposed on the gate electrode, the second ILD layer is disposed on the first ILD layer, and the third ILD layer is disposed on the second ILD layer. The source electrode and the drain electrode are disposed on the third ILD layer, wherein the source electrode and the drain electrode are electrically connected to the patterned semiconductor layer via a first contact window and a second contact window respectively.

Abstract translation: 像素结构包括衬底，图案化半导体层，绝缘层，栅电极，第一层间电介质（ILD）层，第二ILD层，第三ILD层，源电极和漏电极。 图案化半导体层设置在基板上。 绝缘层设置在图案化的半导体层上。 栅电极设置在绝缘层上。 第一ILD层设置在栅电极上，第二ILD层设置在第一ILD层上，第三ILD层设置在第二ILD层上。 源电极和漏极设置在第三ILD层上，其中源电极和漏电极分别经由第一接触窗口和第二接触窗口电连接到图案化半导体层。