公开(公告)号：US20220299881A1

公开(公告)日：2022-09-22

申请号：US17636103

申请日：2020-08-01

Applicant: ASML NETHERLANDS B.V.

Inventor： Yunan ZHENG ,  Yongfa FAN ,  Mu FENG ,  Leiwu ZHENG ,  Jen-Shiang WANG ,  Ya LUO ,  Chenji ZHANG ,  Jun CHEN ,  Zhenyu HOU ,  Jinze WANG ,  Feng CHEN ,  Ziyang MA ,  Xin GUO ,  Jin CHENG

IPC: G03F7/20

Abstract: A method for generating modified contours and/or generating metrology gauges based on the modified contours. A method of generating metrology gauges for measuring a physical characteristic of a structure on a substrate includes obtaining (i) measured data associated with the physical characteristic of the structure printed on the substrate, and (ii) at least portion of a simulated contour of the structure, the at least a portion of the simulated contour being associated with the measured data; modifying, based on the measured data, the at least a portion of the simulated contour of the structure; and generating the metrology gauges on or adjacent to the modified at least a portion of the simulated contour, the metrology gauges being placed to measure the physical characteristic of the simulated contour of the structure.

公开(公告)号：US20230161269A1

公开(公告)日：2023-05-25

申请号：US17919189

申请日：2021-05-07

Applicant: ASML NETHERLANDS B.V.

Inventor： Jiao HUANG ,  Yunan ZHENG ,  Qian ZHAO ,  Jiao LIANG ,  Yongfa FAN ,  Mu FENG

IPC: G03F7/20 ,  G06T7/11

CPC classification number: G03F7/70633 ,  G03F7/70625 ,  G06T7/11 ,  G06T2207/10061

Abstract: Systems and methods for determining one or more characteristic metrics for a portion of a pattern on a substrate are described. Pattern information for the pattern on the substrate is received. The pattern on the substrate has first and second portions. The first portion of the pattern is blocked, for example with a geometrical block mask, based on the pattern information, such that the second portion of the pattern remains unblocked. The one or more metrics are determined for the unblocked second portion of the pattern. In some embodiments, the first and second portions of the pattern correspond to different exposures in a semiconductor lithography process. The semiconductor lithography process may be a multiple patterning technology process, for example, such as a double patterning process, a triple patterning process, or a spacer double patterning process.

公开(公告)号：US20220276564A1

公开(公告)日：2022-09-01

申请号：US17632632

申请日：2020-07-29

Applicant: ASML NETHERLANDS B.V.

Inventor： Mir Farrokh SHAYEGAN SALEK ,  Rafael C. HOWELL ,  Yunan ZHENG ,  Haiqing WEI ,  Yu CAO

IPC: G03F7/20

Abstract: A method of simulating a pattern to be imaged onto a substrate using a photolithography system, the method includes obtaining a pattern to be imaged onto the substrate, smoothing the pattern, and simulating an image of the smoothed pattern. The smoothing may include application of a graphical low pass filter and the simulating may include application of edge filters from an edge filter library.